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<title>kernel/drivers/gpu/ipu-v3/ipu-pre.c, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
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<updated>2018-02-19T14:12:59Z</updated>
<entry>
<title>gpu: ipu-v3: pre: fix device node leak in ipu_pre_lookup_by_phandle</title>
<updated>2018-02-19T14:12:59Z</updated>
<author>
<name>Tobias Jordan</name>
<email>Tobias.Jordan@elektrobit.com</email>
</author>
<published>2018-02-15T14:34:55Z</published>
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<id>urn:sha1:c795f3052b60b01e80485fad98c53e5e67d093c9</id>
<content type='text'>
Before returning, call of_node_put() for the device node returned by
of_parse_phandle().

Fixes: d2a34232580a ("gpu: ipu-v3: add driver for Prefetch Resolve Engine")
Signed-off-by: Tobias Jordan &lt;Tobias.Jordan@elektrobit.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: pre: add tiled prefetch support</title>
<updated>2017-12-19T11:49:11Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-11-10T16:09:58Z</published>
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<id>urn:sha1:2f64a554435da851a9593115b96bdc67e455047a</id>
<content type='text'>
This configures the TPR unit, using the DRM format modifier. For now only
the single buffer modifiers are supported, as split buffer needs more
configuration for the required cropping.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
[p.zabel@pengutronix.de: rebased after ERR009624 workaround]
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: pre: implement workaround for ERR009624</title>
<updated>2017-10-11T10:04:24Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-09-18T15:45:07Z</published>
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<id>urn:sha1:11aff4b4c7c4b7257660ef890920f2ac72911ed0</id>
<content type='text'>
The PRE has a bug where a software write to the CTRL register can block
the setting of the ENABLE bit by the hardware in auto repeat mode. When
this happens the PRE will fail to handle new jobs. To work around this
software must not write to CTRL register when the PRE store engine is
inside the unsafe window, where a hardware update to the ENABLE bit
may happen.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
[p.zabel@pengutronix.de: rebased before PRE tiled prefetch support]
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: pre: only use internal clock gating</title>
<updated>2017-06-06T08:21:10Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-05-03T08:38:18Z</published>
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<content type='text'>
By setting the SFTRST bit, the PRE will be held in the lowest power state
with clocks to the internal blocks gated. When external clock gating is
used (from the external clock controller, or by setting the CLKGATE bit)
the PRE will sporadically fail to start.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Fixes: d2a34232580a ("gpu: ipu-v3: add driver for Prefetch Resolve Engine")
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: add driver for Prefetch Resolve Engine</title>
<updated>2017-03-15T14:42:35Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-03-08T11:13:14Z</published>
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<id>urn:sha1:d2a34232580a5d2c9f58baa5270836c5c9ab83ba</id>
<content type='text'>
This adds support for the i.MX6 QuadPlus PRE units. Currently only
linear prefetch into SRAM is supported, other modes of operation
like the tiled-to-linear conversion will be added later.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
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