kernel/drivers/gpu/ipu-v3/ipu-cpmem.c, branch linux-6.2.y

gpu: ipu-v3: Fix i.MX IPU-v3 offset calculations for (semi)planar U/V formats

2021-08-16T13:05:22Z

Video captured in 1400x1050 resolution (bytesperline aka stride = 1408 bytes) is invalid. Fix it. Signed-off-by: Krzysztof Halasa Link: https://lore.kernel.org/r/m3y2bmq7a4.fsf@t19.piap.pl [p.zabel@pengutronix.de: added "gpu: ipu-v3:" prefix to commit description] Signed-off-by: Philipp Zabel

gpu: ipu-v3: enable remaining 32-bit RGB V4L2 pixel formats

2019-08-19T14:08:55Z

Support is already implemented for the corresponding DRM formats, just hook up the remaining V4L2 pixel formats. Signed-off-by: Philipp Zabel Reviewed-by: Marco Felsch

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 159

2019-05-30T18:26:37Z

Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Richard Fontana Reviewed-by: Allison Randal Reviewed-by: Kate Stewart Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman

media: gpu: ipu-v3: Add planar support to interlaced scan

2019-01-16T19:12:20Z

To support interlaced scan with planar formats, cpmem SLUV must be programmed with the correct chroma line stride. For full and partial planar 4:2:2 (YUV422P, NV16), chroma line stride must be doubled. For full and partial planar 4:2:0 (YUV420, YVU420, NV12), chroma line stride must _not_ be doubled, since a single chroma line is shared by two luma lines. Signed-off-by: Steve Longerbeam Reviewed-by: Philipp Zabel Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

gpu: ipu-v3: Add chroma plane offset overrides to ipu_cpmem_set_image()

2018-11-05T13:40:06Z

Allow the caller of ipu_cpmem_set_image() to override the latters calculation of the chroma plane offsets, by adding override U/V plane offsets to 'struct ipu_image'. Signed-off-by: Steve Longerbeam Tested-by: Philipp Zabel Signed-off-by: Philipp Zabel

gpu: ipu-cpmem: add WARN_ON_ONCE() for unaligned dma buffers

2018-11-05T13:40:06Z

Add a WARN_ON_ONCE() if either the Y/packed buffer, or the U/V offsets, are not aligned on 8-byte boundaries. This will catch alignment bugs in DRM, V4L2. Signed-off-by: Steve Longerbeam Tested-by: Philipp Zabel Signed-off-by: Philipp Zabel

Merge tag 'imx-drm-fixes-2018-08-03' of git://git.pengutronix.de/git/pza/linux into drm-next

2018-08-10T01:37:35Z

drm/imx: ipu-v3 plane offset and IPU id fixes - Fix U/V plane offsets for odd vertical offsets. Due to wrong operator order, the y offset was not rounded down properly for vertically chroma subsampled planar formats. - Fix IPU id number for boards that don't have an OF alias for their single IPU in the device tree. This is necessary to support imx-media on i.MX51 and i.MX53 SoCs. Signed-off-by: Dave Airlie From: Philipp Zabel Link: https://patchwork.freedesktop.org/patch/msgid/1533552680.4204.14.camel@pengutronix.de

gpu: ipu-v3: Fix U/V offset macros for planar 4:2:0

2018-08-02T09:47:39Z

The U and V offset macros for planar 4:2:0 (U_OFFSET, V_OFFSET, and UV_OFFSET), are not correct. The height component to the offset was calculated as: (pix->width * y / 4) But this does not produce correct offsets for odd values of y (luma line #). The luma line # must be decimated by two to produce the correct U/V line #, so the correct formula is: (pix->width * (y / 2) / 2) Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel

gpu: ipu-v3: add support for XRGB32 and XBGR32 V4L2 pixel formats

2018-08-02T09:32:40Z

These should be used instead of the ill-defined deprecated RGB32 and BGR32 V4L2 pixel formats. Signed-off-by: Philipp Zabel

gpu: ipu-v3: Allow negative offsets for interlaced scanning

2018-07-16T14:56:37Z

The IPU also supports interlaced buffers that start with the bottom field. To achieve this, the the base address EBA has to be increased by a stride length and the interlace offset ILO has to be set to the negative stride. Signed-off-by: Philipp Zabel Signed-off-by: Steve Longerbeam