<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/ipu-v3/ipu-common.c, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
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<updated>2018-02-16T13:47:43Z</updated>
<entry>
<title>gpu: ipu-v3: make const arrays int_reg static, shrinks object size</title>
<updated>2018-02-16T13:47:43Z</updated>
<author>
<name>Colin Ian King</name>
<email>colin.king@canonical.com</email>
</author>
<published>2018-02-14T18:45:59Z</published>
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<id>urn:sha1:ac66b8347bbad5913df098e5281fa6e2c7fc796e</id>
<content type='text'>
Don't populate the const read-only arrays int_reg on the stack but instead
make them static. Makes the object code smaller by over 80 bytes:

Before:
   text	   data	    bss	    dec	    hex	filename
  28024	   8936	    192	  37152	   9120	drivers/gpu/ipu-v3/ipu-common.o

After:
   text	   data	    bss	    dec	    hex	filename
  27794	   9080	    192	  37066	   90ca	drivers/gpu/ipu-v3/ipu-common.o

(gcc version 7.2.0 x86_64)

Signed-off-by: Colin Ian King &lt;colin.king@canonical.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Allow channel burst locking on i.MX6 only</title>
<updated>2017-10-11T08:45:06Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2017-10-10T13:13:55Z</published>
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<id>urn:sha1:cda77556447c782b3c9c068f81ef58136cb487c3</id>
<content type='text'>
The IDMAC_LOCK_EN registers on i.MX51 have a different layout, and on
i.MX53 enabling the lock feature causes bursts to get lost. Restrict
enabling the burst lock feature to i.MX6.

Reported-by: Patrick Brünn &lt;P.Bruenn@beckhoff.com&gt;
Fixes: 790cb4c7c954 ("drm/imx: lock scanout transfers for consecutive bursts")
Tested-by: Patrick Brünn &lt;P.Bruenn@beckhoff.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm: Convert to using %pOF instead of full_name</title>
<updated>2017-07-26T11:45:06Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2017-07-18T21:43:04Z</published>
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<id>urn:sha1:4bf99144d2b407bf393e5a7663fe1ed69c646269</id>
<content type='text'>
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Russell King &lt;linux@armlinux.org.uk&gt;
Cc: David Airlie &lt;airlied@linux.ie&gt;
Cc: Daniel Vetter &lt;daniel.vetter@intel.com&gt;
Cc: Jani Nikula &lt;jani.nikula@linux.intel.com&gt;
Cc: Sean Paul &lt;seanpaul@chromium.org&gt;
Cc: Inki Dae &lt;inki.dae@samsung.com&gt;
Cc: Joonyoung Shim &lt;jy0922.shim@samsung.com&gt;
Cc: Seung-Woo Kim &lt;sw0312.kim@samsung.com&gt;
Cc: Kyungmin Park &lt;kyungmin.park@samsung.com&gt;
Cc: Kukjin Kim &lt;kgene@kernel.org&gt;
Cc: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Cc: Javier Martinez Canillas &lt;javier@osg.samsung.com&gt;
Cc: Xinliang Liu &lt;z.liuxinliang@hisilicon.com&gt;
Cc: Rongrong Zou &lt;zourongrong@gmail.com&gt;
Cc: Xinwei Kong &lt;kong.kongxinwei@hisilicon.com&gt;
Cc: Chen Feng &lt;puck.chen@hisilicon.com&gt;
Cc: CK Hu &lt;ck.hu@mediatek.com&gt;
Cc: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Cc: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Cc: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Cc: Carlo Caione &lt;carlo@caione.org&gt;
Cc: Kevin Hilman &lt;khilman@baylibre.com&gt;
Cc: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Cc: Laurent Pinchart &lt;laurent.pinchart@ideasonboard.com&gt;
Cc: Mark Yao &lt;mark.yao@rock-chips.com&gt;
Cc: Heiko Stuebner &lt;heiko@sntech.de&gt;
Cc: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Cc: Chen-Yu Tsai &lt;wens@csie.org&gt;
Cc: Jyri Sarha &lt;jsarha@ti.com&gt;
Cc: Tomi Valkeinen &lt;tomi.valkeinen@ti.com&gt;
Cc: dri-devel@lists.freedesktop.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Partially-Reviewed-by: Laurent Pinchart &lt;laurent.pinchart@ideasonboard.com&gt;
Reviewed-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
[seanpaul changed subject prefix and fixed conflict in stm/ltdc.c]
Signed-off-by: Sean Paul &lt;seanpaul@chromium.org&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>BackMerge tag 'v4.12-rc5' into drm-next</title>
<updated>2017-06-16T03:58:27Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2017-06-16T03:58:27Z</published>
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<id>urn:sha1:925344ccc91d7a7fd84cab2dece1c34bbd86fd8c</id>
<content type='text'>
Linux 4.12-rc5 for nouveau fixes
</content>
</entry>
<entry>
<title>gpu: ipu-v3: remove interrupt busy waiting routine</title>
<updated>2017-06-08T06:57:19Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2017-05-15T14:31:37Z</published>
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<id>urn:sha1:ffb40733fe432b00fa12ff486364dcfe6d7f247c</id>
<content type='text'>
This is not used anymore since commit eb8c88808c83 ("drm/imx: add
deferred plane disabling"), remove it.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: allocate ipuv3_channels as needed</title>
<updated>2017-06-08T06:57:19Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2017-05-08T10:45:52Z</published>
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<id>urn:sha1:93adc8b5705c14d16be382d43699d2ba71248a4b</id>
<content type='text'>
Most of the 64 IPUv3 DMA channels are never used, some of them (channels
16, 30, 32, 34-39, and 53-63) are even marked as reserved.
Allocate the channel control structure only when a channel is actually
requested, replace the fixed size array with a list, and remove the
unused enabled and busy fields from the ipuv3_channel structure.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Fix CSI selection for VDIC</title>
<updated>2017-06-06T08:21:34Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2017-06-03T18:57:21Z</published>
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<id>urn:sha1:b7dfee2433576f1f030cb84cdb04b70f36554992</id>
<content type='text'>
The description of the CSI_SEL bit in the i.MX6 reference manual is
incorrect. It states "This bit defines which CSI is the input to the
IC. This bit is effective only if IC_INPUT is bit cleared".

From experiment it was found this is in fact not correct. The CSI_SEL
bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the
IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC
ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC
receives from in that case.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: don't depend on DRM being enabled</title>
<updated>2017-04-04T08:58:56Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-03-23T15:52:02Z</published>
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<id>urn:sha1:30310c835f3ebfefcf83f006981faa66d73bd810</id>
<content type='text'>
The PRE/PRG drivers, which need the DRM infrastructure, are only used
from the output path, so we skip building them into the ipu-v3 driver
if CONFIG_DRM is not enabled.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: hook up PRG unit</title>
<updated>2017-03-16T09:14:39Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-03-08T11:13:18Z</published>
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<id>urn:sha1:92681fe7e98eb8c0a3ef6e850db399b2de192562</id>
<content type='text'>
The i.MX6 QuadPlus IPU needs to PRG unit to gain access to the
data bus. Make sure it is present and available to be used.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: add driver for Prefetch Resolve Gasket</title>
<updated>2017-03-16T09:14:02Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2017-03-08T11:13:16Z</published>
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<id>urn:sha1:ea9c260514c15f14d43a4c099646c44238dccf1e</id>
<content type='text'>
This adds support for the i.MX6 QUadPlus PRG unit. It glues together the
IPU and the PRE units.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
---
v4: add missing ipu_soc-&gt;prg_priv
</content>
</entry>
</feed>
