<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/ipu-v3/ipu-common.c, branch linux-4.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y'/>
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<updated>2015-01-27T15:28:01Z</updated>
<entry>
<title>gpu: ipu-v3: Fix IC control register offset</title>
<updated>2015-01-27T15:28:01Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2014-09-22T15:15:40Z</published>
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<id>urn:sha1:a49e7c0d079610062048a4ed1cff2bb09436127c</id>
<content type='text'>
The IC register offset is at +0x20000 relative to the control module
registers on all IPUv3 versions. This patch fixes wrong values for
i.MX51 and i.MX53.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'ipu-fixes-3.18' of git://git.pengutronix.de/git/pza/linux into drm-next</title>
<updated>2014-10-07T04:31:14Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2014-10-07T04:31:14Z</published>
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<id>urn:sha1:46d987af7649ef9b2f1d1467b9249fb6e24d2658</id>
<content type='text'>
IPUv3 fixes for v3.18

* tag 'ipu-fixes-3.18' of git://git.pengutronix.de/git/pza/linux:
  gpu: ipu-v3: Kconfig: Remove SOC_IMX6SL from IMX_IPUV3_CORE Kconfig
  gpu: ipu-v3: ipu-smfc: Do not leave DEBUG defined
  gpu: ipu-v3: Return proper error on ipu_add_client_devices error path
  gpu: ipu-v3: Select GENERIC_IRQ_CHIP to fix build error
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add ipu_dump()</title>
<updated>2014-09-02T12:55:56Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2014-06-26T01:05:55Z</published>
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<id>urn:sha1:3feb049f378da6aa1209e05ef5c656a1f26a9183</id>
<content type='text'>
Adds ipu_dump() which dumps IPU register state to debug.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add more planar formats support</title>
<updated>2014-09-02T12:55:55Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2014-06-26T01:05:53Z</published>
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<id>urn:sha1:9a34cef01392358421b764645073601c352d0a85</id>
<content type='text'>
Adds support for the following planar and partial-planar formats:

YUV422
NV12
NV16

Signed-off-by: Dmitry Eremin-Solenikov &lt;dmitry_eremin@mentor.com&gt;
Signed-off-by: Mohsin Kazmi &lt;mohsin_kazmi@mentor.com&gt;
Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;

Unified base offset and Y plane offset into a single variable,
moved all ipu_cpmem_set_buffer calls to a single location.
Removed NV21 and NV61 for now. The IDMAC doesn't understand U/V
order for chroma interleaved formats, so we'd need to work around
this by implenting U/V switching via the CSC unit.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add ipu_idmac_lock_enable()</title>
<updated>2014-09-02T12:55:51Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2014-06-26T01:05:45Z</published>
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<id>urn:sha1:4fd1a07af59bf5e1cfb73f7035bf525522cebc76</id>
<content type='text'>
Adds ipu_idmac_lock_enable(), which enables or disables channel
burst locking.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add ipu_idmac_enable_watermark()</title>
<updated>2014-09-02T12:55:50Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2014-06-26T01:05:44Z</published>
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<id>urn:sha1:2bcf577eb6361827f8347529803528031033cb83</id>
<content type='text'>
Adds the function ipu_idmac_enable_watermark(), which enables or disables
watermarking in the IDMAC channel. Enabling watermarking can increase a
channel's AXI bus arbitration priority.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add ipu_stride_to_bytes()</title>
<updated>2014-09-02T12:55:50Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2014-06-26T01:05:43Z</published>
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<id>urn:sha1:6930afdccfd2b3e6669c305d97958d81cf0d072e</id>
<content type='text'>
Adds ipu_stride_to_bytes(), which converts a pixel stride to bytes,
suitable for passing to cpmem.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add __ipu_idmac_reset_current_buffer()</title>
<updated>2014-09-02T12:55:49Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2014-06-26T01:05:42Z</published>
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<id>urn:sha1:e7268c699bbe578e6dcf02e9f7f5a267837bc18f</id>
<content type='text'>
Adds __ipu_idmac_reset_current_buffer() that resets a channel's
internal current buffer pointer so that transfers start from buffer
0 on the next channel enable.

This operation is required for channel linking to work correctly,
for instance video capture pipelines that carry out image rotations
will fail after the first streaming unless this function is called
for each channel before re-enabling the channels.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add ipu_idmac_clear_buffer()</title>
<updated>2014-09-02T12:55:49Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2014-06-26T01:05:41Z</published>
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<id>urn:sha1:bce6f087a958a21500c51a9e63a5f578f5b0510c</id>
<content type='text'>
Add the reverse of ipu_idmac_select_buffer(), that is, clear a buffer
ready status in a channel.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Add ipu_idmac_buffer_is_ready()</title>
<updated>2014-09-02T12:55:48Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2014-06-26T01:05:40Z</published>
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<id>urn:sha1:aa52f57894b93dcfdd615b35a7579e161f1e7a38</id>
<content type='text'>
Add ipu_idmac_buffer_is_ready(), returns true if the given buffer in
the given channel is set ready (owned by IPU), or false if not ready
(owned by CPU core).

Support has been added for third buffer, there is no support yet for
triple-buffering in idmac channels, but this function checks
buffer-ready for third buffer in case this support is added later.

Signed-off-by: Steve Longerbeam &lt;steve_longerbeam@mentor.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
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