<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/host1x/mipi.c, branch linux-6.9.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.9.y</id>
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<updated>2023-04-04T12:24:24Z</updated>
<entry>
<title>gpu: host1x: mipi: Use devm_platform_get_and_ioremap_resource()</title>
<updated>2023-04-04T12:24:24Z</updated>
<author>
<name>Ye Xingchen</name>
<email>ye.xingchen@zte.com.cn</email>
</author>
<published>2023-02-08T07:41:56Z</published>
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<id>urn:sha1:791b5ecece5e6c22aa9aa55b7a9ee827a971a799</id>
<content type='text'>
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.

Signed-off-by: Ye Xingchen &lt;ye.xingchen@zte.com.cn&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>media: gpu: host1x: mipi: Keep MIPI clock enabled and mutex locked till calibration done</title>
<updated>2020-08-28T13:12:38Z</updated>
<author>
<name>Sowjanya Komatineni</name>
<email>skomatineni@nvidia.com</email>
</author>
<published>2020-08-12T00:27:19Z</published>
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<id>urn:sha1:cf5153e4338c4cca655a4a4eff6d54c6a0adcdb7</id>
<content type='text'>
With the split of MIPI calibration into tegra_mipi_calibrate() and
tegra_mipi_wait(), MIPI clock is not kept enabled and mutex is not locked
till the calibration is done.

So, this patch keeps MIPI clock enabled and mutex locked after triggering
start of calibration till its done.

To let calibration process go through its finite sequence codes before
calibration logic waiting for pads idle state added wait time of 75usec
to make sure it sees idle state to apply the results.

This patch renames tegra_mipi_calibrate() as tegra_mipi_start_calibration()
and tegra_mipi_wait() as tegra_mipi_finish_calibration() to be inline
with their usage.

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab+huawei@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Split tegra_mipi_calibrate() and tegra_mipi_wait()</title>
<updated>2020-07-17T14:06:14Z</updated>
<author>
<name>Sowjanya Komatineni</name>
<email>skomatineni@nvidia.com</email>
</author>
<published>2020-07-15T04:20:53Z</published>
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<id>urn:sha1:b3f1b760710f2acfc04abefc09358c26a75e7e89</id>
<content type='text'>
SW can trigger MIPI pads calibration any time after power on
but calibration results will be latched and applied to the pads
by MIPI CAL unit only when the link is in LP-11 state and then
status register will be updated.

For CSI, trigger of pads calibration happen during CSI stream
enable where CSI receiver is kept ready prior to sensor or CSI
transmitter stream start.

So, pads may not be in LP-11 at this time and waiting for the
calibration to be done immediate after calibration start will
result in timeout.

This patch splits tegra_mipi_calibrate() and tegra_mipi_wait()
so triggering for calibration and waiting for it to complete can
happen at different stages.

Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Use readl_relaxed_poll_timeout() in tegra_mipi_wait()</title>
<updated>2020-07-17T14:06:13Z</updated>
<author>
<name>Sowjanya Komatineni</name>
<email>skomatineni@nvidia.com</email>
</author>
<published>2020-07-15T04:20:52Z</published>
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<id>urn:sha1:7d1409826d95216782b514f102889ed6e71abc04</id>
<content type='text'>
Use readl_relaxed_poll_timeout() in tegra_mipi_wait() to simplify
the code.

Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Update tegra_mipi_request() to be node based</title>
<updated>2020-07-17T14:06:13Z</updated>
<author>
<name>Sowjanya Komatineni</name>
<email>skomatineni@nvidia.com</email>
</author>
<published>2020-07-15T04:20:51Z</published>
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<id>urn:sha1:767598d447aa46411289c5808b0e45e20a1823b4</id>
<content type='text'>
Tegra CSI driver need a separate MIPI device for each channel as
calibration of corresponding MIPI pads for each channel should
happen independently.

So, this patch updates tegra_mipi_request() API to add a device_node
pointer argument to allow creating mipi device for specific device
node rather than a device.

Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dsi: Enhance runtime power management</title>
<updated>2016-08-24T13:58:57Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-08-12T14:00:53Z</published>
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<id>urn:sha1:87904c3e82319cf2bad8d656d79c5030dab9490e</id>
<content type='text'>
The MIPI DSI output on Tegra SoCs requires some external logic to
calibrate the MIPI pads before a video signal can be transmitted. This
MIPI calibration logic requires to be powered on while the MIPI pads are
being used, which is currently done as part of the DSI driver's probe
implementation.

This is suboptimal because it will leave the MIPI calibration logic
powered up even if the DSI output is never used.

On Tegra114 and earlier this behaviour also causes the driver to hang
while trying to power up the MIPI calibration logic because the power
partition that contains the MIPI calibration logic will be powered on
by the display controller at output pipeline configuration time. Thus
the power up sequence for the MIPI calibration logic happens before
it's power partition is guaranteed to be enabled.

Fix this by splitting up the API into a request/free pair of functions
that manage the runtime dependency between the DSI and the calibration
modules (no registers are accessed) and a set of enable, calibrate and
disable functions that program the MIPI calibration logic at points in
time where the power partition is really enabled.

While at it, make sure that the runtime power management also works in
ganged mode, which is currently also broken.

Reported-by: Jonathan Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jonathan Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Power down regulators when unused</title>
<updated>2015-08-13T11:47:21Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-10T09:29:41Z</published>
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<id>urn:sha1:15372d4be7f099662dc84e4e35e844bd4373d959</id>
<content type='text'>
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Add Tegra210 support</title>
<updated>2015-08-13T11:47:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:23:20Z</published>
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<id>urn:sha1:5e7752436e10427ba598de4f2f6b7889daf586cc</id>
<content type='text'>
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Add Tegra132 support</title>
<updated>2015-08-13T11:47:19Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:20:32Z</published>
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<id>urn:sha1:7fd3ecad3f768fd2b39fc4db12044437fbf5d735</id>
<content type='text'>
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Constify OF match table</title>
<updated>2015-08-13T11:47:18Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:19:19Z</published>
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<id>urn:sha1:c22fb79099dbec82b8280106c43f6e800ecc854c</id>
<content type='text'>
This table is never modified and can therefore reside in read-only
memory.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
