kernel/drivers/gpu/host1x/mipi.c, branch linux-4.16.y

drm/tegra: dsi: Enhance runtime power management

2016-08-24T13:58:57Z

The MIPI DSI output on Tegra SoCs requires some external logic to calibrate the MIPI pads before a video signal can be transmitted. This MIPI calibration logic requires to be powered on while the MIPI pads are being used, which is currently done as part of the DSI driver's probe implementation. This is suboptimal because it will leave the MIPI calibration logic powered up even if the DSI output is never used. On Tegra114 and earlier this behaviour also causes the driver to hang while trying to power up the MIPI calibration logic because the power partition that contains the MIPI calibration logic will be powered on by the display controller at output pipeline configuration time. Thus the power up sequence for the MIPI calibration logic happens before it's power partition is guaranteed to be enabled. Fix this by splitting up the API into a request/free pair of functions that manage the runtime dependency between the DSI and the calibration modules (no registers are accessed) and a set of enable, calibrate and disable functions that program the MIPI calibration logic at points in time where the power partition is really enabled. While at it, make sure that the runtime power management also works in ganged mode, which is currently also broken. Reported-by: Jonathan Hunter Tested-by: Jonathan Hunter Signed-off-by: Thierry Reding

gpu: host1x: mipi: Power down regulators when unused

2015-08-13T11:47:21Z

Keep track of the number of users of DSI and CSI pads and power down the regulators that supply the bricks when all users are gone. Signed-off-by: Thierry Reding

gpu: host1x: mipi: Add Tegra210 support

2015-08-13T11:47:20Z

Some changes are needed to the configuration settings for some lanes. In addition, the clock lanes for the CSI pads can no longer be calibrated. Signed-off-by: Thierry Reding

gpu: host1x: mipi: Add Tegra132 support

2015-08-13T11:47:19Z

While Tegra132 has the same pads as Tegra124, some configuration values need to be programmed slightly differently. Signed-off-by: Thierry Reding

gpu: host1x: mipi: Constify OF match table

2015-08-13T11:47:18Z

This table is never modified and can therefore reside in read-only memory. Signed-off-by: Thierry Reding

gpu: host1x: mipi: Clear calibration status

2015-08-13T11:47:17Z

Before starting a new calibration cycle, make sure to clear the current status by writing a 1 to the various "calibration done" bits. Signed-off-by: Thierry Reding

gpu: host1x: mipi: Fix clock lane register for DSI

2015-08-13T11:47:16Z

Use more consistent names for the clock lane configuration registers and fix the offset of the upper clock lane configuration register for the first DSI pad. Signed-off-by: Thierry Reding

gpu: host1x: mipi: Parameterize to support future SoCs

2015-08-13T11:47:15Z

Parameterize more of the register programming to accomodate for changes required by future SoC generations. Signed-off-by: Thierry Reding

gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register

2014-11-13T15:11:57Z

During calibration, sets the "internal reference level for drive pull- down" to the value specified in the Tegra TRM. Signed-off-by: Sean Paul Signed-off-by: Thierry Reding

gpu: host1x: mipi: Calibrate clock lanes

2014-11-13T15:11:54Z

Include the clock lanes when calibrating the MIPI PHY on Tegra124 compatible devices. Signed-off-by: Sean Paul [treding@nvidia.com: bikeshedding] Signed-off-by: Thierry Reding