<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/host1x/hw/syncpt_hw.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2017-10-20T12:19:52Z</updated>
<entry>
<title>gpu: host1x: Enable Tegra186 syncpoint protection</title>
<updated>2017-10-20T12:19:52Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2017-09-28T12:50:39Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=c3f52220f276504dea5615cc78750ddc9f468389'/>
<id>urn:sha1:c3f52220f276504dea5615cc78750ddc9f468389</id>
<content type='text'>
Since Tegra186 the Host1x hardware allows syncpoints to be assigned to
specific channels, preventing any other channels from incrementing
them.

Enable this feature where available and assign syncpoints to channels
when submitting a job. Syncpoints are currently never unassigned from
channels since that would require extra work and is unnecessary with
the current channel allocation model.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Fix bitshift/mask multipliers</title>
<updated>2017-08-17T15:57:06Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2017-08-02T09:55:05Z</published>
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<id>urn:sha1:4ac45eb8d17c1a998182c302bd023ecb055bd9ee</id>
<content type='text'>
Some parts of Host1x uses BIT_WORD/BIT_MASK/BITS_PER_LONG to calculate
register or field offsets. This worked fine on ARMv7, but now that
BITS_PER_LONG is 64 but our registers are still 32-bit things are
broken.

Fix by replacing..
- BIT_WORD with (x / 32)
- BIT_MASK with BIT(x % 32)
- BITS_PER_LONG with 32

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Whitespace cleanup for readability</title>
<updated>2016-06-23T09:59:30Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-23T09:35:50Z</published>
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<id>urn:sha1:0b8070d12ee2ef62e0b07213d843eb508fba966e</id>
<content type='text'>
Insert a number of blank lines in places where they increase readability
of the code. Also collapse various variable declarations to shorten some
functions and finally rewrite some code for readability.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Fix a couple of checkpatch warnings</title>
<updated>2016-06-23T09:59:28Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-23T09:33:31Z</published>
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<id>urn:sha1:6df633d0dc333ffce683f46f2856024479b170b9</id>
<content type='text'>
Fix a couple of occurrences where no blank line was used to separate
variable declarations from code or where block comments were wrongly
formatted.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Consistently use unsigned int for counts</title>
<updated>2016-06-23T09:59:23Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-22T14:44:07Z</published>
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<id>urn:sha1:14c95fc896e1d3929abde448fd86c07bdbae56d5</id>
<content type='text'>
The number of channels, syncpoints, bases and mlocks can never be
negative, so use unsigned int instead of int. Also make loop variables
the same type for consistency.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Use relative include paths</title>
<updated>2013-10-31T08:55:40Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-10-09T08:32:54Z</published>
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<id>urn:sha1:fc3be3e8fc8b3b6e800d6dc8ffb794e9d27ba5d2</id>
<content type='text'>
This is slightly safer than adding -Idrivers/gpu/host1x to cflags-y.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Rework CPU syncpoint increment</title>
<updated>2013-06-22T10:43:55Z</updated>
<author>
<name>Arto Merilainen</name>
<email>amerilainen@nvidia.com</email>
</author>
<published>2013-05-29T10:26:08Z</published>
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<id>urn:sha1:ebae30b1fbcc2cc991ce705cc82e16d1e5ddbf51</id>
<content type='text'>
This patch merges host1x_syncpt_cpu_incr to host1x_syncpt_incr() as
they are in practise doing the same thing. host1x_syncpt_incr() is
also modified to return error codes. User space interface is modified
accordingly to pass return values.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Acked-By: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add debug support</title>
<updated>2013-04-22T10:32:46Z</updated>
<author>
<name>Terje Bergstrom</name>
<email>tbergstrom@nvidia.com</email>
</author>
<published>2013-03-22T14:34:04Z</published>
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<id>urn:sha1:6236451d83a720072053855fa63d51934024a707</id>
<content type='text'>
Add support for host1x debugging. Adds debugfs entries, and dumps
channel state to UART in case of stuck job.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add channel support</title>
<updated>2013-04-22T10:32:43Z</updated>
<author>
<name>Terje Bergstrom</name>
<email>tbergstrom@nvidia.com</email>
</author>
<published>2013-03-22T14:34:03Z</published>
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<id>urn:sha1:6579324a41cc414009a601738b70a53d6376325c</id>
<content type='text'>
Add support for host1x client modules, and host1x channels to submit
work to the clients.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add host1x driver</title>
<updated>2013-04-22T10:32:40Z</updated>
<author>
<name>Terje Bergstrom</name>
<email>tbergstrom@nvidia.com</email>
</author>
<published>2013-03-22T14:34:01Z</published>
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<id>urn:sha1:754716874389ccbea5ee03174df8ad9e72e41880</id>
<content type='text'>
Add host1x, the driver for host1x and its client unit 2D. The Tegra
host1x module is the DMA engine for register access to Tegra's
graphics- and multimedia-related modules. The modules served by
host1x are referred to as clients. host1x includes some other
functionality, such as synchronization.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
</content>
</entry>
</feed>
