<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/tegra/sor.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
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<updated>2018-01-17T23:32:15Z</updated>
<entry>
<title>BackMerge tag 'v4.15-rc8' into drm-next</title>
<updated>2018-01-17T23:32:15Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2018-01-17T23:32:15Z</published>
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<id>urn:sha1:4a6cc7a44e98a0460bd094b68c75f0705fdc450a</id>
<content type='text'>
Linux 4.15-rc8

Daniel requested this for so the intel CI won't fall over on drm-next
so often.
</content>
</entry>
<entry>
<title>drm/tegra: sor: Fix hang on Tegra124 eDP</title>
<updated>2018-01-10T12:04:58Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-01-10T12:04:58Z</published>
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<id>urn:sha1:d780537f9b49e9d714a454e5ed989d909beab8ec</id>
<content type='text'>
The SOR0 found on Tegra124 and Tegra210 only supports eDP and LVDS and
therefore has a slightly different clock tree than the SOR1 which does
not support eDP, but HDMI and DP instead.

Commit e1335e2f0cfc ("drm/tegra: sor: Reimplement pad clock") breaks
setups with eDP because the sor-&gt;clk_out clock is uninitialized and
therefore setting the parent clock (either the safe clock or either of
the display PLLs) fails, which can cause hangs later on since there is
no clock driving the module.

Fix this by falling back to the module clock for sor-&gt;clk_out on those
setups. This guarantees that the module will always be clocked by an
enabled clock and hence prevents those hangs.

Fixes: e1335e2f0cfc ("drm/tegra: sor: Reimplement pad clock")
Reported-by: Guillaume Tucker &lt;guillaume.tucker@collabora.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Use direct offset to plane registers</title>
<updated>2017-12-21T13:52:34Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-12-14T12:37:53Z</published>
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<id>urn:sha1:1087fac18b8e3ec8fadf1595bbc46dce7ff08a81</id>
<content type='text'>
Traditionally, windows were accessed indirectly, through a register
selection window that required a global register to be programmed with
the index of the window to access. Since the global register could be
written from modesetting functions as well as the interrupt handler
concurrently, accesses had to be serialized using a lock. Using direct
accesses to the window registers the lock can be avoided.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: sor: Support HDMI 2.0 modes</title>
<updated>2017-12-13T13:36:37Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-10-12T17:14:21Z</published>
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<id>urn:sha1:36e90221acf37dd0eb5dee70cd189cc60f2e501a</id>
<content type='text'>
In addition to using the SCDC helpers to enable support for scrambling
for HDMI 2.0 modes, take into account the high pixel clocks when
programming some of the registers.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: sor: Add Tegra186 support</title>
<updated>2017-12-13T13:36:36Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-10-12T17:12:57Z</published>
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<id>urn:sha1:c57997bce423fb71334a1fefa524569e48a1718f</id>
<content type='text'>
The SOR found on Tegra186 is very similar to the one found on Tegra210
and earlier. However, due to some changes in the display architecture,
some programming sequences have changed and some register have moved
around.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: sor: Parameterize register offsets</title>
<updated>2017-12-13T13:16:39Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-10-12T17:04:17Z</published>
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<id>urn:sha1:880cee0b7ff379ebcf1f3d839fa59d1bcd726797</id>
<content type='text'>
Future Tegra generations have an increased number of display controllers
that can drive individual SORs. In order to support that, the offset and
layout of some registers has changed in backwards-incompatible ways. Use
parameterized register offsets to support this.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: sor: Register debugfs in -&gt;late_register()</title>
<updated>2017-12-13T12:42:08Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-11-08T12:20:01Z</published>
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<id>urn:sha1:5b8e043b6df4caf4aa41921ed584659a0c5ad269</id>
<content type='text'>
The -&gt;late_register() and -&gt;early_unregister() callbacks are called at
the right time to make sure userspace only accesses interfaces when it
should. Move debugfs registration and unregistration to these callback
functions to avoid potential races with userspace.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: sor: Root debugfs files at the connector</title>
<updated>2017-12-13T12:42:08Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-10-12T17:07:54Z</published>
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<id>urn:sha1:d92e600998d83569cc0955a63c5f036867336343</id>
<content type='text'>
Rather create new files within the top-level DRM device's debugfs node,
add the SOR specific files to the connector's debugfs node. This avoids
the need to come up with subdirectory names and is also more intuitive.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: sor: Move register definitions into a table</title>
<updated>2017-12-13T12:42:06Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-11-10T11:21:51Z</published>
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<id>urn:sha1:062f5b2c423ce6069b385745153938cf74013d4a</id>
<content type='text'>
After commit 932f6529139e ("drm/tegra: sor: Trace register accesses"),
the debugfs register dump implementation causes excessive stack usage
and can result in build warnings. To fix this, move the register
definitions into a table and iterate over the table while dumping the
registers to debugfs.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: sor: Reimplement pad clock</title>
<updated>2017-11-20T12:23:54Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-10-12T15:53:11Z</published>
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<id>urn:sha1:e1335e2f0cfcd36ffa1b709ac58096134eb6e779</id>
<content type='text'>
The current implementation of the pad clock isn't quite correct. This
has the side-effect of being incompatible with the implementation for
Tegra186 (provided by the BPMP) and therefore would require a massive
change to the driver to cope with the differences. Instead, simply do
what Tegra186 does and add some code to fallback to the old behaviour
for existing device trees.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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