<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/tegra/hdmi.c, branch linux-4.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y</id>
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<updated>2015-04-02T16:49:23Z</updated>
<entry>
<title>drm/tegra: hdmi: Name register fields consistently</title>
<updated>2015-04-02T16:49:23Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-01-28T15:32:52Z</published>
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<id>urn:sha1:5c1c071a3667600d1b8426dba031b2d4a20a3efa</id>
<content type='text'>
Name the fields of the SOR_SEQ_CTL register consistently.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: hdmi: Resets are synchronous</title>
<updated>2015-04-02T16:49:22Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-01-28T15:14:26Z</published>
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<id>urn:sha1:375e118437716acdccda224abb3d464ecfe92884</id>
<content type='text'>
Resets on Tegra are synchronous, so keep the clock enabled while
asserting the reset.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: hdmi: Explicitly set clock rate</title>
<updated>2015-02-19T13:21:25Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-02-18T09:34:08Z</published>
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<id>urn:sha1:c03bf1bfd3a5448a4474f02b839f2195e3719cd9</id>
<content type='text'>
Recent changes in the clock framework have caused a behavioural change
in that clocks that have not had their rate set explicitly will now be
reset to their initial rate (or 0) when the clock is released. This is
triggered in the deferred probing path, resulting in the clock running
at a wrong frequency after the successful probe.

This can be easily fixed by setting the rate explicitly rather than by
relying on the implicit rate inherited by the parent.

Tested-by: Tomeu Vizoso &lt;tomeu.vizoso@collabora.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Unify enabling the display controller</title>
<updated>2015-01-27T09:14:58Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-08T15:32:47Z</published>
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<id>urn:sha1:666cb873328b5075eb511662858bab02d084ff64</id>
<content type='text'>
Previously output drivers would enable continuous display mode and power
up the display controller at various points during the initialization.
This is suboptimal because it accesses display controller registers in
output drivers and duplicates a bit of code.

Move this code into the display controller driver and enable the display
controller as the final step of the -&gt;mode_set_nofb() implementation.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Remove unused -&gt;mode_fixup() callbacks</title>
<updated>2015-01-27T09:14:56Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-19T14:19:21Z</published>
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<id>urn:sha1:3f0fb52ef013e76159b35386f22924f99d8034a4</id>
<content type='text'>
All output drivers have now been converted to use the -&gt;atomic_check()
callback, so the -&gt;mode_fixup() callbacks are no longer used.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: hdmi: Implement -&gt;atomic_check()</title>
<updated>2015-01-27T09:14:53Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-08T15:33:03Z</published>
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<id>urn:sha1:a9825a6e27a81dac1641ef13fae8b480d7d11d5f</id>
<content type='text'>
The implementation of the -&gt;atomic_check() callback precomputes all
parameters to check if the given configuration can be applied. If so the
precomputed values are stored in the atomic state object for the encoder
and applied during modeset. In that way the modeset no longer needs to
perform any checking but simply program values into registers.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Atomic conversion, phase 2</title>
<updated>2015-01-27T09:14:51Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-11-24T16:02:53Z</published>
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<id>urn:sha1:9d44189f55c77face595982bad3310bd4078b9fe</id>
<content type='text'>
Hook up the default -&gt;reset() and -&gt;atomic_duplicate_state() helpers.
This ensures that state objects are properly created and framebuffer
reference counts correctly maintained.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Atomic conversion, phase 1</title>
<updated>2015-01-27T09:14:50Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-11-24T15:27:13Z</published>
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<id>urn:sha1:4aa3df7149a00cb061d2ba74e2136cd14a6d885a</id>
<content type='text'>
Implement initial atomic state handling. Hook up the CRTCs, planes' and
connectors' -&gt;atomic_destroy_state() callback to ensure that the atomic
state objects don't leak.

Furthermore the CRTC now implements the -&gt;mode_set_nofb() callback that
is used by new helpers to implement -&gt;mode_set() and -&gt;mode_set_base().
These new helpers also make use of the new plane helper functions which
the driver now provides.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Output cleanup functions cannot fail</title>
<updated>2015-01-27T09:14:49Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-19T14:55:08Z</published>
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<id>urn:sha1:328ec69e7f9e7192c3f7653a5ec46d6e9a5fe60d</id>
<content type='text'>
The tegra_output_exit() and tegra_output_remove() functions cannot fail,
so make them return void.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Remove remnants of the output midlayer</title>
<updated>2015-01-27T09:14:49Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-19T14:51:35Z</published>
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<id>urn:sha1:ea130b240de820559408eba12b00412326af36ec</id>
<content type='text'>
The tegra_output midlayer is now completely gone and output drivers use
it purely as a helper library.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
