<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/tegra/gem.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
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<updated>2018-03-08T13:38:30Z</updated>
<entry>
<title>drm/tegra: gem: Make __tegra_gem_mmap() available more widely</title>
<updated>2018-03-08T13:38:30Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-02-07T17:45:55Z</published>
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<id>urn:sha1:04c0746663bd3ae3cce5e02d5b32c8ade2a833b8</id>
<content type='text'>
This function allows mapping a GEM object into a virtual memory address
space, which makes it useful outside of the GEM code.

While at it, rename the function so it doesn't clash with the function
that implements the DRM_TEGRA_GEM_MMAP IOCTL.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gem: Reshuffle declarations</title>
<updated>2018-03-08T13:38:05Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-02-07T17:45:54Z</published>
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<id>urn:sha1:b6d7974d10b30bf3baed7e50d8e574f5184cfdd1</id>
<content type='text'>
Move declarations in the gem.h header file into the same order as the
corresponding definitions in gem.c.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Use .dumb_map_offset and .dumb_destroy defaults</title>
<updated>2017-08-16T18:13:48Z</updated>
<author>
<name>Noralf Trønnes</name>
<email>noralf@tronnes.org</email>
</author>
<published>2017-08-06T15:40:55Z</published>
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<id>urn:sha1:bcf877181eb5439074bf6312e42087d988413adb</id>
<content type='text'>
This driver can use the drm_driver.dumb_destroy and
drm_driver.dumb_map_offset defaults, so no need to set them.

Cc: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Signed-off-by: Noralf Trønnes &lt;noralf@tronnes.org&gt;
Reviewed-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/1502034068-51384-7-git-send-email-noralf@tronnes.org
</content>
</entry>
<entry>
<title>drm/tegra: Check for malformed offsets and sizes in the 'submit' IOCTL</title>
<updated>2017-06-15T12:16:07Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2017-06-14T23:18:26Z</published>
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<id>urn:sha1:368f622c0d76a22662af33759be8c4408819295d</id>
<content type='text'>
If commands buffer claims a number of words that is higher than its BO can
fit, a kernel OOPS will be fired on the out-of-bounds BO access. This was
triggered by an opentegra Xorg driver that erroneously pushed too many
commands to the pushbuf.

The CDMA commands buffer address is 4 bytes aligned, so check its
alignment.

The maximum number of the CDMA gather fetches is 16383, add a check for
it.

Add a sanity check for the relocations in a same way.

[   46.829393] Unable to handle kernel paging request at virtual address f09b2000
...
[&lt;c04a3ba4&gt;] (host1x_job_pin) from [&lt;c04dfcd0&gt;] (tegra_drm_submit+0x474/0x510)
[&lt;c04dfcd0&gt;] (tegra_drm_submit) from [&lt;c04deea0&gt;] (tegra_submit+0x50/0x6c)
[&lt;c04deea0&gt;] (tegra_submit) from [&lt;c04c07c0&gt;] (drm_ioctl+0x1e4/0x3ec)
[&lt;c04c07c0&gt;] (drm_ioctl) from [&lt;c02541a0&gt;] (do_vfs_ioctl+0x9c/0x8e4)
[&lt;c02541a0&gt;] (do_vfs_ioctl) from [&lt;c0254a1c&gt;] (SyS_ioctl+0x34/0x5c)
[&lt;c0254a1c&gt;] (SyS_ioctl) from [&lt;c0107640&gt;] (ret_fast_syscall+0x0/0x3c)

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gem: Use more consistent data types</title>
<updated>2014-11-13T15:18:32Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-11-03T12:23:02Z</published>
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<id>urn:sha1:71c38629d6bd4be74009fc73946255254477c77e</id>
<content type='text'>
Use size_t consistently for sizes and u32/u64 instead of uint32_t and
uint64_t.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add IOMMU support</title>
<updated>2014-11-13T15:14:48Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-26T19:41:53Z</published>
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<id>urn:sha1:df06b759f2cf4690fa9991edb1504ba39932b2bb</id>
<content type='text'>
When an IOMMU device is available on the platform bus, allocate an IOMMU
domain and attach the display controllers to it. The display controllers
can then scan out non-contiguous buffers by mapping them through the
IOMMU.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm: Extract &lt;drm/drm_gem.h&gt;</title>
<updated>2014-09-24T01:43:41Z</updated>
<author>
<name>Daniel Vetter</name>
<email>daniel.vetter@ffwll.ch</email>
</author>
<published>2014-09-23T13:46:53Z</published>
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<id>urn:sha1:d9fc9413f97f5c615256a5657ec667c064c07a70</id>
<content type='text'>
v2: Don't forget git add, noticed by David.

Cc: David Herrmann &lt;dh.herrmann@gmail.com&gt;

Signed-off-by: Daniel Vetter &lt;daniel.vetter@intel.com&gt;
Acked-by: David Herrmann &lt;dh.herrmann@gmail.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Implement more tiling modes</title>
<updated>2014-08-04T08:07:34Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-03T12:48:12Z</published>
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<id>urn:sha1:c134f019abcfaa1cb6e07f6154e92a4f8ce8ddd8</id>
<content type='text'>
Tegra124 supports a block-linear mode in addition to the regular pitch
linear and tiled modes. Add support for these by moving the internal
representation into a structure rather than a simple flag.

Tested-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Relicense under GPL v2</title>
<updated>2014-04-04T07:12:51Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-02-11T14:52:01Z</published>
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<id>urn:sha1:9a2ac2dcdc4baa63c913377f9856993498398025</id>
<content type='text'>
The majority of the code in this driver is licensed under the GPL v2, so
relicense the rest under GPL v2 as well for consistency.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add PRIME support</title>
<updated>2013-12-20T14:56:07Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-12-12T09:00:43Z</published>
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<id>urn:sha1:3800391db1b22a7f5d5ae92f9c54fa00327d682a</id>
<content type='text'>
Implement very basic PRIME support. This currently only works with
buffers that are contiguous in memory and will refuse to import any
physically non-contiguous buffers.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
