kernel/drivers/gpu/drm/tegra/gem.h, branch linux-4.1.yHosts the 0x221E linux distro kernel.https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y2014-11-13T15:18:32Zdrm/tegra: gem: Use more consistent data types2014-11-13T15:18:32ZThierry Redingtreding@nvidia.com2014-11-03T12:23:02Zurn:sha1:71c38629d6bd4be74009fc73946255254477c77e
Use size_t consistently for sizes and u32/u64 instead of uint32_t and
uint64_t.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Add IOMMU support2014-11-13T15:14:48ZThierry Redingtreding@nvidia.com2014-06-26T19:41:53Zurn:sha1:df06b759f2cf4690fa9991edb1504ba39932b2bb
When an IOMMU device is available on the platform bus, allocate an IOMMU
domain and attach the display controllers to it. The display controllers
can then scan out non-contiguous buffers by mapping them through the
IOMMU.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm: Extract <drm/drm_gem.h>2014-09-24T01:43:41ZDaniel Vetterdaniel.vetter@ffwll.ch2014-09-23T13:46:53Zurn:sha1:d9fc9413f97f5c615256a5657ec667c064c07a70
v2: Don't forget git add, noticed by David.
Cc: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Acked-by: David Herrmann <dh.herrmann@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drm/tegra: Implement more tiling modes2014-08-04T08:07:34ZThierry Redingtreding@nvidia.com2014-06-03T12:48:12Zurn:sha1:c134f019abcfaa1cb6e07f6154e92a4f8ce8ddd8
Tegra124 supports a block-linear mode in addition to the regular pitch
linear and tiled modes. Add support for these by moving the internal
representation into a structure rather than a simple flag.
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Relicense under GPL v22014-04-04T07:12:51ZThierry Redingtreding@nvidia.com2014-02-11T14:52:01Zurn:sha1:9a2ac2dcdc4baa63c913377f9856993498398025
The majority of the code in this driver is licensed under the GPL v2, so
relicense the rest under GPL v2 as well for consistency.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Add PRIME support2013-12-20T14:56:07ZThierry Redingtreding@nvidia.com2013-12-12T09:00:43Zurn:sha1:3800391db1b22a7f5d5ae92f9c54fa00327d682a
Implement very basic PRIME support. This currently only works with
buffers that are contiguous in memory and will refuse to import any
physically non-contiguous buffers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Do not export tegra_bo_ops2013-12-19T08:29:54ZThierry Redingtreding@nvidia.com2013-12-12T09:10:46Zurn:sha1:425c0fdc427440fdaf039a649eab713d932fa368
These buffer object operations are never used outside of the GEM
implementation so there is no use in exporting them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Support bottom-up buffer objects2013-10-31T08:55:46ZThierry Redingthierry.reding@avionic-design.de2013-10-07T07:47:58Zurn:sha1:db7fbdfd25ee009165b6c3b80a9d1c6d8534ad94
The gr3d engine renders images bottom-up. Allow buffers that are used
for 3D content to be marked as such and implement support in the display
controller to present them properly.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Add support for tiled buffer objects2013-10-31T08:55:46ZThierry Redingthierry.reding@avionic-design.de2013-10-04T20:34:01Zurn:sha1:773af77fc479fd454c3f6836f86bf63996545cf4
The gr2d and gr3d engines work more efficiently on buffers with a tiled
memory layout. Allow created buffers to be marked as tiled so that the
display controller can scan them out properly.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: Move driver to DRM tree2013-10-31T08:55:40ZThierry Redingtreding@nvidia.com2013-10-09T08:32:49Zurn:sha1:dee8268f8fb218c9e9b604a40f7dbdd395e910f9
In order to make subsystem-wide changes easier, move the Tegra DRM
driver back into the DRM tree.
Signed-off-by: Thierry Reding <treding@nvidia.com>