kernel/drivers/gpu/drm/tegra/dsi.c, branch linux-4.17.y

drm/tegra: dsi: Don't disable regulator on ->exit()

2018-03-19T08:57:28Z

The regulator is controlled as part of runtime PM, so it should not be additionally disabled from the ->exit() callback. Signed-off-by: Thierry Reding

drm/tegra: dsi: Register debugfs in ->late_register()

2017-12-13T12:42:07Z

The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding

drm/tegra: dsi: Move register definitions into a table

2017-12-13T12:42:04Z

After commit 75af8fa7fd47 ("drm/tegra: dsi: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding

Merge tag 'drm/tegra/for-4.14-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

2017-08-21T07:37:33Z

drm/tegra: Changes for v4.14-rc1 This contains a couple of fixes and improvements for host1x, with some preparatory work for Tegra186 support. The remainder is cleanup and minor bugfixes for Tegra DRM along with enhancements to debuggability. There have also been some enhancements to the kernel interfaces for host1x job submissions and support for mmap'ing PRIME buffers directly, all of which get the interfaces very close to ready for serious work. * tag 'drm/tegra/for-4.14-rc1' of git://anongit.freedesktop.org/tegra/linux: (21 commits) drm/tegra: Prevent BOs from being freed during job submission drm/tegra: gem: Implement mmap() for PRIME buffers drm/tegra: Support render node drm/tegra: sor: Trace register accesses drm/tegra: dpaux: Trace register accesses drm/tegra: dsi: Trace register accesses drm/tegra: hdmi: Trace register accesses drm/tegra: dc: Trace register accesses drm/tegra: sor: Use unsigned int for register offsets drm/tegra: hdmi: Use unsigned int for register offsets drm/tegra: dsi: Use unsigned int for register offsets drm/tegra: dpaux: Use unsigned int for register offsets drm/tegra: dc: Use unsigned int for register offsets drm/tegra: Fix NULL deref in debugfs/iova drm/tegra: switch to drm_*_get(), drm_*_put() helpers drm/tegra: Set MODULE_FIRMWARE for the VIC drm/tegra: Add CONFIG_OF dependency gpu: host1x: Support sub-devices recursively gpu: host1x: fix error return code in host1x_probe() gpu: host1x: Fix bitshift/mask multipliers ...

drm/tegra: dsi: Trace register accesses

2017-08-17T15:57:16Z

Add tracepoint events for DSI controller register accesses. Signed-off-by: Thierry Reding

drm/tegra: dsi: Use unsigned int for register offsets

2017-08-17T15:57:13Z

Register offsets are usually fairly small numbers, so an unsigned int is more than enough to represent them. Signed-off-by: Thierry Reding

drm: Nuke drm_atomic_helper_connector_dpms

2017-08-08T12:48:48Z

It's dead code, the core handles all this directly now. The only special case is nouveau and tda988x which used one function for both legacy modeset code and -nv50 atomic world instead of 2 vtables. But amounts to exactly the same. v2: Rebase over the panel/brideg refactorings in stm/ltdc. Signed-off-by: Daniel Vetter Cc: Archit Taneja Cc: Andrzej Hajda Cc: Laurent Pinchart Cc: Peter Senna Tschudin Cc: Martin Donnelly Cc: Martyn Welch Cc: Daniel Vetter Cc: Jani Nikula Cc: Sean Paul Cc: David Airlie Cc: Inki Dae Cc: Joonyoung Shim Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: Stefan Agner Cc: Alison Wang Cc: Russell King Cc: Philipp Zabel Cc: CK Hu Cc: Matthias Brugger Cc: Neil Armstrong Cc: Carlo Caione Cc: Kevin Hilman Cc: Marek Vasut Cc: Ben Skeggs Cc: Tomi Valkeinen Cc: Eric Anholt Cc: Mark Yao Cc: Heiko Stuebner Cc: Benjamin Gaignard Cc: Vincent Abriou Cc: Yannick Fertre Cc: Philippe Cornu Cc: Maxime Ripard Cc: Chen-Yu Tsai Cc: Thierry Reding Cc: Jonathan Hunter Cc: Jyri Sarha Cc: Gerd Hoffmann Cc: Shawn Guo Cc: John Stultz Cc: Lars-Peter Clausen Cc: Sergei Shtylyov Cc: Jeffy Chen Cc: Tomeu Vizoso Cc: Yakir Yang Cc: Marek Szyprowski Cc: Jose Abreu Cc: Romain Perier Cc: Kieran Bingham Cc: Xinliang Liu Cc: Alexey Brodkin Cc: Alex Deucher Cc: Rongrong Zou Cc: Rob Clark Cc: Hai Li Cc: "Noralf Trønnes" Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: intel-gfx@lists.freedesktop.org Cc: linux-mediatek@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: nouveau@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-tegra@vger.kernel.org Cc: virtualization@lists.linux-foundation.org Cc: zain wang Cc: Baoyou Xie Cc: Boris Brezillon Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170725080122.20548-8-daniel.vetter@ffwll.ch Acked-by: Neil Armstrong Reviewed-by: Neil Armstrong Acked-by: Philipp Zabel Acked-by: Archit Taneja Tested-by: Philippe Cornu (on stm) Reviewed-by: Laurent Pinchart Acked-by: Shawn Guo Acked-by: Shawn Guo Acked-by: Noralf Trønnes Acked-by: Vincent Abriou

drm/tegra: dsi: Enhance runtime power management

2016-08-24T13:58:57Z

The MIPI DSI output on Tegra SoCs requires some external logic to calibrate the MIPI pads before a video signal can be transmitted. This MIPI calibration logic requires to be powered on while the MIPI pads are being used, which is currently done as part of the DSI driver's probe implementation. This is suboptimal because it will leave the MIPI calibration logic powered up even if the DSI output is never used. On Tegra114 and earlier this behaviour also causes the driver to hang while trying to power up the MIPI calibration logic because the power partition that contains the MIPI calibration logic will be powered on by the display controller at output pipeline configuration time. Thus the power up sequence for the MIPI calibration logic happens before it's power partition is guaranteed to be enabled. Fix this by splitting up the API into a request/free pair of functions that manage the runtime dependency between the DSI and the calibration modules (no registers are accessed) and a set of enable, calibrate and disable functions that program the MIPI calibration logic at points in time where the power partition is really enabled. While at it, make sure that the runtime power management also works in ganged mode, which is currently also broken. Reported-by: Jonathan Hunter Tested-by: Jonathan Hunter Signed-off-by: Thierry Reding

Merge tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

2016-07-16T01:23:50Z

drm/tegra: Changes for v4.8-rc1 This set of changes contains a bunch of cleanups to the host1x driver as well as the addition of a pin controller for DPAUX, which is required by boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C mode (for HDMI and DDC). Included is also a bit of rework of the SOR driver in preparation to add DisplayPort support as well as some refactoring and cleanup. Finally, all output drivers are converted to runtime PM, which greatly simplifies the handling of clocks and resets. * tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits) drm/tegra: sor: Reject HDMI 2.0 modes drm/tegra: sor: Prepare for generic PM domain support drm/tegra: dsi: Prepare for generic PM domain support drm/tegra: sor: Make XBAR configurable per SoC drm/tegra: sor: Use sor1_src clock to set parent for HDMI dt-bindings: display: tegra: Add source clock for SOR drm/tegra: sor: Implement sor1_brick clock drm/tegra: sor: Implement runtime PM drm/tegra: hdmi: Implement runtime PM drm/tegra: dsi: Implement runtime PM drm/tegra: dc: Implement runtime PM drm/tegra: hdmi: Enable audio over HDMI drm/tegra: sor: Do not support deep color modes drm/tegra: sor: Extract tegra_sor_mode_set() drm/tegra: sor: Split out tegra_sor_apply_config() drm/tegra: sor: Rename tegra_sor_calc_config() drm/tegra: sor: Factor out tegra_sor_set_parent_clock() drm/tegra: dpaux: Add pinctrl support dt-bindings: Add bindings for Tegra DPAUX pinctrl driver drm/tegra: Prepare DPAUX for supporting generic PM domains ...

drm/tegra: dsi: Prepare for generic PM domain support

2016-07-14T12:57:02Z

The DSI driver for Tegra requires the SOR power partition to be enabled. Now that Tegra supports the generic PM domain framework we manage the SOR power partition via this framework. However, the sequence for gating/ungating the SOR power partition requires that the DSI reset is asserted/de-asserted at the time the SOR power partition is gated/ungated, respectively. Now that the reset control core assumes that resets are exclusive, the Tegra generic PM domain code and the DSI driver cannot request the same reset unless we mark the reset as shared. Sharing resets will not work in this case because we cannot guarantee that the reset will be asserted/de-asserted at the appropriate time. Therefore, given that the Tegra generic PM domain code will handle the resets, do not request the reset in the DSI driver if the DSI device has a PM domain associated. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding