<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/tegra/dpaux.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
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<updated>2017-12-21T13:52:37Z</updated>
<entry>
<title>drm/tegra: dpaux: Keep reset defaults for hybrid pad parameters</title>
<updated>2017-12-21T13:52:37Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-12-14T12:25:37Z</published>
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<id>urn:sha1:72ba4cf52410c0426a299f2ac82acd38c27c8207</id>
<content type='text'>
Keep the reset values for the common mode voltage, output driver
impedance control and output driver current control parameters. This
fixes errors seen during SCDC communication with HDMI sinks.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Add Tegra186 support</title>
<updated>2017-12-13T13:36:38Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-10-12T15:34:11Z</published>
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<id>urn:sha1:7b2c2845e5d59db1d9dfa822436a71b2de18a7ee</id>
<content type='text'>
DPAUX is the same as on previous generations. Supporting it is as simple
as adding the compatible string so that the driver will bind to any of
the devices.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Implement runtime PM</title>
<updated>2017-12-13T13:36:38Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-10-12T15:32:52Z</published>
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<id>urn:sha1:82b81b3ec1a796d10206fd8333437db20ef215fc</id>
<content type='text'>
Move clock and reset management into runtime PM callbacks and hook them
up. This cleans up the code structure so that power management code does
not clutter up the rest.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Trace register accesses</title>
<updated>2017-08-17T15:57:16Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-08-15T13:41:13Z</published>
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<id>urn:sha1:eba7c4551a9b07bf68126e4f22fec4b66475f529</id>
<content type='text'>
Add tracepoint events for DPAUX controller register accesses.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Use unsigned int for register offsets</title>
<updated>2017-08-17T15:57:12Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-08-15T13:41:06Z</published>
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<id>urn:sha1:e8ddfdcbea4ff7a902b8508b0c51c45da444fd8a</id>
<content type='text'>
Register offsets are usually fairly small numbers, so an unsigned int is
more than enough to represent them.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Fix error handling</title>
<updated>2016-11-07T11:58:12Z</updated>
<author>
<name>Christophe Jaillet</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2016-10-28T09:09:45Z</published>
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<id>urn:sha1:9376cad2073d2c122864754ea5f80025c8507b0b</id>
<content type='text'>
The devm_pinctrl_register() function returns an error pointer or a valid
handle. So checking for NULL here is pointless and can never trigger.

Check the returned value with IS_ERR instead and propagate this value as
done in the other functions which call devm_pinctrl_register().

Fixes: 0751bb5c44fe ("drm/tegra: dpaux: Add pinctrl support")
Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Add pinctrl support</title>
<updated>2016-06-30T20:13:14Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2016-06-29T09:17:55Z</published>
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<id>urn:sha1:0751bb5c44fe1aa9494ce259d974c3d249b73a84</id>
<content type='text'>
The DPAUX pins are shared with an internal I2C controller. To allow
these pins to be muxed to the I2C controller, register a pinctrl device
for the DPAUX device.

This is based upon work by Thierry Reding &lt;treding@nvidia.com&gt;.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Prepare DPAUX for supporting generic PM domains</title>
<updated>2016-06-30T10:44:50Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2016-06-29T09:17:51Z</published>
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<id>urn:sha1:9b99044afc125c9dc6f739272d8b6f945a066064</id>
<content type='text'>
To utilise the DPAUX on Tegra, the SOR power partition must be enabled.
Now that Tegra supports the generic PM domain framework we manage the
SOR power partition via this framework for DPAUX. However, the sequence
for gating/ungating the SOR power partition requires that the DPAUX
reset is asserted/de-asserted at the time the SOR power partition is
gated/ungated, respectively. Now that the reset control core assumes
that resets are exclusive, the Tegra generic PM domain code and the
DPAUX driver cannot request the same reset unless we mark the resets as
shared. Sharing resets will not work in this case because we cannot
guarantee that the reset will be asserted/de-asserted at the appropriate
time. Therefore, given that the Tegra generic PM domain code will handle
the DPAUX reset, do not request the reset in the DPAUX driver if the
DPAUX device has a PM domain associated.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Add helpers for setting up pads</title>
<updated>2016-06-30T10:40:37Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2016-06-29T09:17:49Z</published>
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<id>urn:sha1:9d0e09c15c4c8d73a83b5244a33732a7b82c52cd</id>
<content type='text'>
In preparation for adding pinctrl support for the DPAUX pads, add a
couple of helpers functions to configure the pads and control their
power.

Please note that although a simple if-statement could be used instead
of a case statement for configuring the pads as there are only two
possible modes, a case statement is used because when integrating with
the pinctrl framework, we need to be able to handle invalid modes that
could be passed.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dpaux: Clean-up on probe failure</title>
<updated>2016-06-30T10:30:43Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2016-06-29T09:17:48Z</published>
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<id>urn:sha1:bcbd63dfc90a3ae515013b0f300e4f3ce62f7249</id>
<content type='text'>
If the probing of the DPAUX fails, then clocks are left enabled and the
DPAUX reset de-asserted. Add code to perform the necessary clean-up on
probe failure by disabling clocks and asserting the reset.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
