<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/tegra/dc.h, branch linux-4.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y</id>
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<updated>2015-04-02T16:46:21Z</updated>
<entry>
<title>drm/tegra: dc: Implement hardware VBLANK counter</title>
<updated>2015-04-02T16:46:21Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-01-28T13:43:05Z</published>
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<id>urn:sha1:42e9ce0523699b3f3383b7c5c0bcc2657a77d0ca</id>
<content type='text'>
The display controller on Tegra can use syncpoints to count VBLANK
events. syncpoints are 32-bit unsigned integers, so well suited as
VBLANK counters.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Implement more tiling modes</title>
<updated>2014-08-04T08:07:34Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-03T12:48:12Z</published>
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<id>urn:sha1:c134f019abcfaa1cb6e07f6154e92a4f8ce8ddd8</id>
<content type='text'>
Tegra124 supports a block-linear mode in addition to the regular pitch
linear and tiled modes. Add support for these by moving the internal
representation into a structure rather than a simple flag.

Tested-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add hardware cursor support</title>
<updated>2014-06-05T21:14:47Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-12-20T12:58:33Z</published>
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<id>urn:sha1:e687651bc1ed96b0ad2ee9464f341c53563b5353</id>
<content type='text'>
Enable hardware cursor support on Tegra124. Earlier generations support
the hardware cursor to some degree as well, but not in a way that can be
generically exposed.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc - Rename INVERT_V to V_DIRECTION</title>
<updated>2014-06-05T21:09:17Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-02-25T11:04:06Z</published>
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<id>urn:sha1:eba66501ac41b717d60bebc6f9ae0f3195c6c422</id>
<content type='text'>
V_DIRECTION is the name of the field in the documentation, so use that
for consistency. Also add the H_DIRECTION field for completeness.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add eDP support</title>
<updated>2014-04-04T07:12:50Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-11-15T15:06:05Z</published>
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<id>urn:sha1:6b6b604215c64666fbf0fed939a5c312cc7b12fe</id>
<content type='text'>
Add support for eDP functionality found on Tegra124 and later SoCs. Only
fast link training is currently supported.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Relocate some output-specific code</title>
<updated>2013-12-20T14:56:07Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-12-12T10:06:55Z</published>
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<id>urn:sha1:72d302861530bcdb780ea57ebfc3dff6ec4f802c</id>
<content type='text'>
Some of the code in the CRTC's mode setting code is specific to the RGB
output or needs to be called slightly differently depending on the type
of output. Push that code down into the output drivers.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add Tegra124 DC support</title>
<updated>2013-12-20T14:56:06Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-12-12T10:03:59Z</published>
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<id>urn:sha1:8620fc629aeec02ac3b3735703940696386a3039</id>
<content type='text'>
Tegra124 and later support interlacing, but the driver doesn't support
it yet. Make sure interlacing stays disabled on hardware that supports
it.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add DSI support</title>
<updated>2013-12-20T14:56:04Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-09-03T06:45:46Z</published>
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<id>urn:sha1:dec727399a4b36bec87b7b4d4c1b20025e69758a</id>
<content type='text'>
This commit adds support for both DSI outputs found on Tegra. Only very
minimal functionality is implemented, so advanced features like ganged
mode won't work.

Due to the lack of other test hardware, some sections of the driver are
hardcoded to work with Dalmore.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Support bottom-up buffer objects</title>
<updated>2013-10-31T08:55:46Z</updated>
<author>
<name>Thierry Reding</name>
<email>thierry.reding@avionic-design.de</email>
</author>
<published>2013-10-07T07:47:58Z</published>
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<id>urn:sha1:db7fbdfd25ee009165b6c3b80a9d1c6d8534ad94</id>
<content type='text'>
The gr3d engine renders images bottom-up. Allow buffers that are used
for 3D content to be marked as such and implement support in the display
controller to present them properly.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add support for tiled buffer objects</title>
<updated>2013-10-31T08:55:46Z</updated>
<author>
<name>Thierry Reding</name>
<email>thierry.reding@avionic-design.de</email>
</author>
<published>2013-10-04T20:34:01Z</published>
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<id>urn:sha1:773af77fc479fd454c3f6836f86bf63996545cf4</id>
<content type='text'>
The gr2d and gr3d engines work more efficiently on buffers with a tiled
memory layout. Allow created buffers to be marked as tiled so that the
display controller can scan them out properly.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
