<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/tegra/dc.c, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
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<updated>2018-11-29T16:25:32Z</updated>
<entry>
<title>drm/tegra: dc: Don't clean up unused display controller</title>
<updated>2018-11-29T16:25:32Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-11-29T16:24:35Z</published>
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<id>urn:sha1:e75d04771ad60cb65005f35a7eb65caa6e7c266c</id>
<content type='text'>
Display controllers that don't own any windows and which therefore
aren't currently being assigned a primary plane are not registered
as a CRTC with the DRM framework. They request neither a syncpoint
nor an interrupt because they don't use them, so avoid cleaning up
those resources.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Add Tegra194 support</title>
<updated>2018-09-26T14:04:39Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-09-21T10:27:44Z</published>
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<id>urn:sha1:474431968507d437d340de35b709aa3b41f8c996</id>
<content type='text'>
The display controllers found on Tegra194 are almost identical to those
found on Tegra186.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Do not register DC without primary plane</title>
<updated>2018-09-26T14:03:51Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-09-21T10:27:42Z</published>
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<id>urn:sha1:759d706f7cb4adbec1c222f7550dc8fa2683c089</id>
<content type='text'>
Tegra194 contains a fourth display controller that does not own any
windows. Therefore, we cannot currently assign a primary plane to it
which causes KMS to eventually crash. Do not register the display
controller if it owns no windows to work around this.

Note that we still have to enable and probe the display controller
because for some reason all display controllers need to be powered
(and/or clocked) before any registers can be accessed in any of the
display controllers.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>driver core: Rename flag AUTOREMOVE to AUTOREMOVE_CONSUMER</title>
<updated>2018-07-09T10:14:31Z</updated>
<author>
<name>Vivek Gautam</name>
<email>vivek.gautam@codeaurora.org</email>
</author>
<published>2018-06-27T12:50:55Z</published>
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<id>urn:sha1:e88728f46cfbb59cc7e7acf1d230c05ec093764e</id>
<content type='text'>
Now that we want to add another flag to autoremove the device link
on supplier unbind, it's fair to rename the existing flag from
DL_FLAG_AUTOREMOVE to DL_FLAG_AUTOREMOVE_CONSUMER so that we can
add similar flag for supplier later.
And, while we are touching device.h, fix a doc build warning.

Signed-off-by: Vivek Gautam &lt;vivek.gautam@codeaurora.org&gt;
Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Support rotation property</title>
<updated>2018-05-18T19:56:21Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-03-19T16:20:46Z</published>
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<id>urn:sha1:995c5a509fb032ddd83eff4f3772c7fc8ff0b7ec</id>
<content type='text'>
Currently only the DRM_MODE_REFLECT_Y rotation is supported. The driver
already supports reflection on the Y axis via a custom flag which is not
very useful because it requires custom userspace. Add the standard
rotation property that supports 0 degree rotation and Y axis reflection
for primary and overlay planes to provide a better interface than the
custom flag.

v2: keep custom flag for ABI compatibility (Dmitry)

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Rename supports_blending to has_legacy_blending</title>
<updated>2018-05-17T12:08:44Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-05-04T14:40:00Z</published>
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<id>urn:sha1:a43d0a00ea58a665905d94e8ab469ff888b1b0e1</id>
<content type='text'>
Older Tegra chips do support blending as well. Rename the SoC info entry
.supports_blending to .has_legacy_blending to eliminate the confusion.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: plane: Implement zpos plane property for older Tegras</title>
<updated>2018-05-17T12:08:44Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-05-04T14:39:59Z</published>
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<id>urn:sha1:3dae08bc076b93487ed2df50bcfa892113e89d9d</id>
<content type='text'>
Older Tegra's do not support plane's Z position handling in hardware,
but the hardware provides knobs to implement it in software.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Enable plane scaling filters</title>
<updated>2018-05-17T12:08:44Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-05-04T14:39:58Z</published>
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<id>urn:sha1:acc6a3a9afdd4e0537342012656cdb5c4a3127c5</id>
<content type='text'>
Currently resized plane produces a "pixelated" image which doesn't look
nice, especially in a case of a video overlay. Enable scaling filters that
significantly improve image quality of a scaled overlay.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Refactor IOMMU attach/detach</title>
<updated>2018-05-17T12:08:40Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-05-04T13:02:24Z</published>
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<id>urn:sha1:0c407de5ed1a329468122cbf4f3e727e0c1e3f36</id>
<content type='text'>
Attaching to and detaching from an IOMMU uses the same code sequence in
every driver, so factor it out into separate helpers.

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: dc: Free syncpoint on errors</title>
<updated>2018-05-04T15:07:06Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-05-04T13:00:54Z</published>
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<id>urn:sha1:fd5ec0dc34dafa6c5bb46770ca283ae90a4db3c7</id>
<content type='text'>
If an error happens during display controller initialization, the host1x
syncpoint previously requested would be leaked. Properly clean up the
syncpoint along with the other resources.

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
