kernel/drivers/gpu/drm/sun4i/sun4i_hdmi.h, branch linux-4.17.y

drm/sun4i: hdmi: Document PAD_CTRL1 output invert bits

2017-10-16T07:54:21Z

While debugging inverted color from the HDMI output on the A10, I found that the lowest 3 bits were set. These were cleared on A20 boards that had normal display output. By manually toggling these bits the mapping of the color components to these bits was found. While these are not used anywhere, it would be nice to document them somewhere. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20171014040252.9621-7-wens@csie.org

drm/sun4i: hdmi: Add support for A31's HDMI controller

2017-10-11T07:53:49Z

The HDMI controller found in the A31 SoCs is slightly different from the one already supported, which is found in the A10s: - Need different initial values for the PLL related registers - Different behavior of the DDC and TMDS clocks - Different register layout for the DDC portion - Separate DDC parent clock This patch adds support for it. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-10-wens@csie.org

drm/sun4i: hdmi: Add A31 specific DDC register definitions

2017-10-11T07:53:41Z

The DDC block for the HDMI controller is different on the A31. This patch adds the register definitions. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-9-wens@csie.org

drm/sun4i: hdmi: Add support for controller hardware variants

2017-10-11T07:53:33Z

The HDMI controller found in earlier Allwinner SoCs have slight differences between the A10, A10s, and the A31: - Need different initial values for the PLL related registers - Different behavior of the DDC and TMDS clocks - Different register layout for the DDC portion - Separate DDC parent clock on the A31 - Explicit reset control For the A31, the HDMI TMDS clock has a different value offset for the divider. The HDMI DDC block is different from the one in the other SoCs. As far as the DDC clock goes, it has no pre-divider, as it is clocked from a slower parent clock, not the TMDS clock. The divider offset from the register value is different. And the clock control register is at a different offset. A new variant data structure is created to store pointers to the above functions, structures, and the different initial values. Another flag notates whether there is a separate DDC parent clock. If not, the TMDS clock is passed to the DDC clock create function, as before. Regmap fields are used to deal with the different register layout of the DDC block. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org

drm/sun4i: hdmi: create a regmap for later use

2017-10-11T07:53:06Z

The HDMI driver is written with readl/writel I/O to the registers. However, to support the A31 variant, which has a different layout for the DDC registers, it was recommended to use regfields to have a cleaner implementation. To use regfields, we need to create an underlying regmap. This patch only adds the regmap. It does not convert the existing driver accesses to use regmap. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-5-wens@csie.org

drm/sun4i: cec: Enable back CEC-pin framework

2017-09-22T06:42:17Z

Now that the cec-pin framework has been merged, we can remove the safeguard that were preventing the CEC part of the sun4i HDMI driver and actually start to use it. Signed-off-by: Hans Verkuil Signed-off-by: Maxime Ripard

sun4i_hdmi: add CEC support

2017-07-18T16:27:50Z

Add HDMI CEC support to the Allwinner A10 SoC. This SoC uses a poor-man's CEC implementation by polling the CEC pin. It is using the CEC_PIN core implementation for such devices to do the heavy lifting. It just provides the callbacks to read/drive the CEC pin. Signed-off-by: Hans Verkuil Tested-by: Maxime Ripard Signed-off-by: Maxime Ripard

drm/sun4i: hdmi: Implement I2C adapter for A10s DDC bus

2017-07-17T06:21:39Z

The documentation for drm_do_get_edid in drivers/gpu/drm/drm_edid.c states: "As in the general case the DDC bus is accessible by the kernel at the I2C level, drivers must make all reasonable efforts to expose it as an I2C adapter and use drm_get_edid() instead of abusing this function." Exposing the DDC bus as an I2C adapter is more beneficial as it can be used for purposes other than reading the EDID such as modifying the EDID or using the HDMI DDC pins as an I2C bus through the I2C dev interface from userspace (e.g. i2c-tools). Implement this for A10s. Signed-off-by: Jonathan Liu Signed-off-by: Maxime Ripard

drm/sun4i: Add HDMI support

2017-06-01T07:50:01Z

The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI controller. That HDMI controller is able to do audio and CEC, but those have been left out for now. Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard