<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/radeon/rv770d.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2016-08-24T20:25:05Z</updated>
<entry>
<title>drm/radeon: switch UVD code to use UVD_NO_OP for padding</title>
<updated>2016-08-24T20:25:05Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-08-23T14:07:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=70a033d25b197b0a4e60509911195613cf28b57e'/>
<id>urn:sha1:70a033d25b197b0a4e60509911195613cf28b57e</id>
<content type='text'>
Replace packet2's with packet0 writes to UVD_NO_OP.  The
value written to UVD_NO_OP does not matter.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: disable semaphores for UVD V1 (v2)</title>
<updated>2015-05-04T19:03:56Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-05-01T10:34:12Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=013ead48a843442e63b9426e3bd5df18ca5d054a'/>
<id>urn:sha1:013ead48a843442e63b9426e3bd5df18ca5d054a</id>
<content type='text'>
Hardware doesn't seem to work correctly, just block userspace in this case.

v2: add missing defines

Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=85320

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
CC: stable@vger.kernel.org
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: implement pci config reset for r6xx/7xx (v3)</title>
<updated>2014-01-08T23:42:22Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-11-01T23:01:36Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=de9ae7447aaa2fed8ae4aa9e6b7260915e5b4f7b'/>
<id>urn:sha1:de9ae7447aaa2fed8ae4aa9e6b7260915e5b4f7b</id>
<content type='text'>
pci config reset is a low level reset that resets
the entire chip from the bus interface.  It can
be more reliable if soft reset fails.

There's not much information still available on
r6xx, so r6xx is based on guess-work.

v2: put behind module parameter
v3: add IGP check

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: Fix hmdi typo</title>
<updated>2013-09-16T00:27:51Z</updated>
<author>
<name>Damien Lespiau</name>
<email>damien.lespiau@intel.com</email>
</author>
<published>2013-09-13T15:37:28Z</published>
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<id>urn:sha1:d592fca9407d065f0754ba29790c66ecbc0366ad</id>
<content type='text'>
I keep making that one, so checked if I was the only one. Apparently
not.

Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Damien Lespiau &lt;damien.lespiau@intel.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: separate UVD code v3</title>
<updated>2013-08-30T20:30:42Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2013-08-13T09:56:53Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e409b128625732926c112cc9b709fb7bb1aa387f'/>
<id>urn:sha1:e409b128625732926c112cc9b709fb7bb1aa387f</id>
<content type='text'>
Our different hardware blocks are actually completely
separated, so it doesn't make much sense any more to
structure the code by pure chipset generations.

Start restructuring the code by separating our the UVD block.

v2: updated commit message
v3: rebased and restructurized start/stop functions for kv dpm.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon/dpm: add debugfs support for 7xx/evergreen/btc</title>
<updated>2013-07-01T20:08:32Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-06-28T14:06:26Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=bd210d11cd37bee3da729e56288b5b4a038f88bd'/>
<id>urn:sha1:bd210d11cd37bee3da729e56288b5b4a038f88bd</id>
<content type='text'>
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon/kms: add dpm support for rv7xx (v4)</title>
<updated>2013-06-27T23:14:59Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-06-26T04:11:19Z</published>
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<id>urn:sha1:66229b200598a3b66b839d1759ff3f5b17ac5639</id>
<content type='text'>
This adds dpm support for rv7xx asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching

Set radeon.dpm=1 to enable.

v2: reduce stack usage
v3: fix 64 bit div
v4: fix state enable

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: fix UPLL_REF_DIV_MASK definition</title>
<updated>2013-05-02T14:09:48Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2013-04-29T08:20:23Z</published>
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<id>urn:sha1:092fbc4ca29a3d78895673479f794ee162a13ac5</id>
<content type='text'>
Stupid copy &amp; paste error over all generations.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: add UVD tiling addr config v2</title>
<updated>2013-04-09T14:31:39Z</updated>
<author>
<name>Christian König</name>
<email>deathsimple@vodafone.de</email>
</author>
<published>2013-04-08T10:41:37Z</published>
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<id>urn:sha1:9a21059dc4c0e80f2eebcb0a9096721ef1dc9c9d</id>
<content type='text'>
v2: set UVD tiling config for rv730

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Jerome Glisse &lt;jglisse@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: add set_uvd_clocks callback for r7xx v3</title>
<updated>2013-04-09T14:31:37Z</updated>
<author>
<name>Christian König</name>
<email>deathsimple@vodafone.de</email>
</author>
<published>2013-04-08T10:41:35Z</published>
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<id>urn:sha1:ef0e6e657cfe6e80036b5263887c6ec102c4bae9</id>
<content type='text'>
v2: avoid 64bit divide
v3: rv740 uses the evegreen upll configuration

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Jerome Glisse &lt;jglisse@redhat.com&gt;
</content>
</entry>
</feed>
