<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/radeon/rs400.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
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<updated>2017-03-30T03:53:24Z</updated>
<entry>
<title>gpu: drm: amd/radeon: Convert printk(KERN_&lt;LEVEL&gt; to pr_&lt;level&gt;</title>
<updated>2017-03-30T03:53:24Z</updated>
<author>
<name>Joe Perches</name>
<email>joe@perches.com</email>
</author>
<published>2017-02-28T12:55:52Z</published>
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<id>urn:sha1:7ca85295d8cc280ea79cf6250c47363b7fd92f92</id>
<content type='text'>
Use a more common logging style.

Miscellanea:

o Coalesce formats and realign arguments
o Neaten a few macros now using pr_&lt;level&gt;

Signed-off-by: Joe Perches &lt;joe@perches.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: Split off gart_get_page_entry ASIC hook from set_page_entry</title>
<updated>2015-01-22T16:46:17Z</updated>
<author>
<name>Michel Dänzer</name>
<email>michel.daenzer@amd.com</email>
</author>
<published>2015-01-21T08:36:35Z</published>
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<id>urn:sha1:cb65890610dca287718a63bd8a5d9ce3dc80c3d7</id>
<content type='text'>
get_page_entry calculates the GART page table entry, which is just written
to the GART page table by set_page_entry.

This is a prerequisite for the following fix.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: Fix typo 'addr' -&gt; 'entry' in rs400_gart_set_page</title>
<updated>2014-09-19T01:52:29Z</updated>
<author>
<name>Michel Dänzer</name>
<email>michel.daenzer@amd.com</email>
</author>
<published>2014-09-19T01:22:46Z</published>
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<id>urn:sha1:226b6d88d0c38bd0817660c79e3bea870dfeee4b</id>
<content type='text'>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83996
Signed-off-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: Pass GART page flags to radeon_gart_set_page() explicitly</title>
<updated>2014-08-05T12:53:32Z</updated>
<author>
<name>Michel Dänzer</name>
<email>michel.daenzer@amd.com</email>
</author>
<published>2014-07-17T10:01:07Z</published>
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<id>urn:sha1:77497f2735ad6e29c55475e15e9790dbfa2c2ef8</id>
<content type='text'>
Signed-off-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: Remove radeon_gart_restore()</title>
<updated>2014-08-05T12:53:31Z</updated>
<author>
<name>Michel Dänzer</name>
<email>michel.daenzer@amd.com</email>
</author>
<published>2014-07-09T18:15:42Z</published>
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<id>urn:sha1:a3eb06dbca08e3fdad7039021ae03b46b215f22a</id>
<content type='text'>
Doesn't seem necessary, the GART table memory should be persistent.

Signed-off-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: remove range check from *_gart_set_page</title>
<updated>2014-06-10T02:06:51Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-06-04T13:29:57Z</published>
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<id>urn:sha1:7f90fc965023d72589a4e5fc02ac812e3a6ac809</id>
<content type='text'>
We never check the return value anyway and if the
index isn't valid would crash way before calling
the functions.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: resume old pm late</title>
<updated>2014-03-06T21:46:56Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2014-02-25T17:01:28Z</published>
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<id>urn:sha1:bc6a62955f6ea6aabe26292a21dbdd67f5b89b67</id>
<content type='text'>
Moving the pm resume up in the init order to fix
dpm seems to have regressed somes cases with the old
pm code.  Move it back to late resume.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon/pm: move pm handling into the asic specific code</title>
<updated>2013-12-24T22:57:06Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-12-18T19:07:14Z</published>
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<id>urn:sha1:6c7bccea390853bdec5b76fe31fc50f3b36f75d5</id>
<content type='text'>
We need more control over the ordering of dpm init with
respect to the rest of the asic.  Specifically, the SMC
has to be initialized before the rlc and cg/pg.  The pm
code currently initializes late in the driver, but we need
it to happen much earlier so move pm handling into the asic
specific callbacks.

This makes dpm more reliable and makes clockgating work
properly on CIK parts and should help on SI parts as well.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: add spinlocks for indirect register accesss</title>
<updated>2013-09-11T15:44:29Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-09-03T23:00:09Z</published>
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<id>urn:sha1:0a5b7b0bd97a212f5d8d28c5011b04a45dfb006e</id>
<content type='text'>
This adds spinlocks to protect access to other
indirect register apertures.  These indirect spaces are
used pretty infrequently and we haven't had an reported
problems, but better safe than sorry.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: fix resume on some rs4xx boards (v2)</title>
<updated>2013-08-30T20:31:09Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-08-26T21:52:12Z</published>
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<id>urn:sha1:acf88deb8ddbb73acd1c3fa32fde51af9153227f</id>
<content type='text'>
Setting MC_MISC_CNTL.GART_INDEX_REG_EN causes hangs on
some boards on resume.  The systems seem to work fine
without touching this bit so leave it as is.

v2: read-modify-write the GART_INDEX_REG_EN bit.
I suspect the problem is that we are losing the other
settings in the register.

fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=52952

Reported-by: Ondrej Zary &lt;linux@rainbow-software.org&gt;
Tested-by: Daniel Tobias &lt;dan.g.tob@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
</feed>
