<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/radeon/nid.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2016-08-24T20:25:05Z</updated>
<entry>
<title>drm/radeon: switch UVD code to use UVD_NO_OP for padding</title>
<updated>2016-08-24T20:25:05Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-08-23T14:07:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=70a033d25b197b0a4e60509911195613cf28b57e'/>
<id>urn:sha1:70a033d25b197b0a4e60509911195613cf28b57e</id>
<content type='text'>
Replace packet2's with packet0 writes to UVD_NO_OP.  The
value written to UVD_NO_OP does not matter.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: implement tn_set_vce_clocks</title>
<updated>2015-05-26T14:31:21Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-05-11T20:01:50Z</published>
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<id>urn:sha1:0fda42ac40ac7edf62ebb750be41a34902d2fdfb</id>
<content type='text'>
This implements the function to set the vce clocks
on TN hardware.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: program auxch directly (v2)</title>
<updated>2015-03-19T16:26:44Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2015-02-19T23:21:36Z</published>
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<id>urn:sha1:875711f0e217b00cba1a851eee01c4e33041a91c</id>
<content type='text'>
The atombios tables have an unfortunate restriction on only
being able to write 12 bytes, MST really wants 16-bytes here,
and since the hw can do it, we should just write directly to it.

This uses a module option to allow for it now, and maybe
we should provide the old code as a fallback for a while.

v2: (agd5f)
- move registers to a proper register header
- only enable on DCE5+
- enable by default on DCE5+
- Switch pad to aux mode before using it
- reformat instance handling to better match the
  rest of the driver

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: add get_allowed_info_register for cayman/TN</title>
<updated>2015-03-19T16:26:40Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2014-10-01T13:51:29Z</published>
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<id>urn:sha1:e66582f9ff2fac4c3fddac4f06ebb0e9623485f5</id>
<content type='text'>
Registers that can be fetched from the info ioctl.

Tested-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: enable SRBM timeout interrupt on EG/NI</title>
<updated>2015-02-25T21:06:08Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-02-18T12:19:28Z</published>
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<id>urn:sha1:acc1522a54a3ff4dc250b6e94c55c53c5240e234</id>
<content type='text'>
Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: fix VM flush on cayman/aruba (v3)</title>
<updated>2015-01-08T14:36:50Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-01-06T00:42:25Z</published>
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<id>urn:sha1:cbfc35b90f3b4853d1eb9fcb82e99531d6a1c629</id>
<content type='text'>
We need to wait for the GPUVM flush to complete.  There
was some confusion as to how this mechanism was supposed
to work.  The operation is not atomic.  For GPU initiated
invalidations you need to read back a VM register to
introduce enough latency for the update to complete.

v2: drop gart changes
v3: just read back rather than polling

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2</title>
<updated>2014-06-02T14:25:03Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2014-05-10T10:17:56Z</published>
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<id>urn:sha1:1c89d27fb9f169003c5a82561ffeb8adb980ebfb</id>
<content type='text'>
This patch makes it possible to decide how many address
bits are spend on the page directory vs the page tables.

v2: remove unintended change

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: fix surface sync in fence on cayman (v2)</title>
<updated>2014-01-20T23:20:56Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2014-01-16T23:02:59Z</published>
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<id>urn:sha1:10e9ffae463396c5a25fdfe8a48d7c98a87f6b85</id>
<content type='text'>
We need to set the engine bit to select the ME and
also set the full cache bit.  Should help stability
on TN and cayman.

V2: fix up surface sync in ib execute as well

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/radeon: add fault decode function for cayman/TN (v2)</title>
<updated>2013-07-14T14:11:28Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-06-13T22:26:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=54e2e49ce28ff7ac67b93e7e9e44702552b04a69'/>
<id>urn:sha1:54e2e49ce28ff7ac67b93e7e9e44702552b04a69</id>
<content type='text'>
Helpful for debugging GPUVM errors as we can see what
hw block and page generated the fault in the log.

v2: simplify fault decoding

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon/dpm: add debugfs support for cayman</title>
<updated>2013-07-01T20:08:57Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-06-28T21:49:02Z</published>
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<id>urn:sha1:bdf0c4f07d5fbda79569a11116053bed44873c8a</id>
<content type='text'>
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
