<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/radeon/evergreend.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2016-08-24T20:25:05Z</updated>
<entry>
<title>drm/radeon: switch UVD code to use UVD_NO_OP for padding</title>
<updated>2016-08-24T20:25:05Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-08-23T14:07:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=70a033d25b197b0a4e60509911195613cf28b57e'/>
<id>urn:sha1:70a033d25b197b0a4e60509911195613cf28b57e</id>
<content type='text'>
Replace packet2's with packet0 writes to UVD_NO_OP.  The
value written to UVD_NO_OP does not matter.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: allow PACKET3_PFP_SYNC_ME on evergreen</title>
<updated>2016-07-07T18:50:59Z</updated>
<author>
<name>Edmondo Tommasina</name>
<email>edmondo.tommasina@gmail.com</email>
</author>
<published>2016-05-30T23:11:14Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=662ce7bce7a4dac4a9587fb78a745c061a402b7f'/>
<id>urn:sha1:662ce7bce7a4dac4a9587fb78a745c061a402b7f</id>
<content type='text'>
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Edmondo Tommasina &lt;edmondo.tommasina@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: add support for SET_APPEND_CNT packet3 (v2)</title>
<updated>2016-05-05T00:19:49Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2016-04-06T20:50:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8c4f2bbd66784f00a509bf0787aa16b19ceaa6c7'/>
<id>urn:sha1:8c4f2bbd66784f00a509bf0787aa16b19ceaa6c7</id>
<content type='text'>
This adds support to the command parser for the set append counter
packet3, this is required to support atomic counters on
evergreen/cayman GPUs.

v2: fixup some of the hardcoded numbers with real register names
(Christian)

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: fix DP audio support for APU with DCE4.1 display engine</title>
<updated>2016-01-27T17:50:25Z</updated>
<author>
<name>Slava Grigorev</name>
<email>slava.grigorev@amd.com</email>
</author>
<published>2016-01-26T22:35:57Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=fe6fc1f132b4300c1f6defd43a5d673eb60a820d'/>
<id>urn:sha1:fe6fc1f132b4300c1f6defd43a5d673eb60a820d</id>
<content type='text'>
Properly setup the DFS divider for DP audio for DCE4.1.

Signed-off-by: Slava Grigorev &lt;slava.grigorev@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/radeon: add get_allowed_info_register for EG/BTC</title>
<updated>2015-03-19T16:26:39Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2014-10-01T13:43:38Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ff609975e1cd8a58ee862fb3188e8b01b935131d'/>
<id>urn:sha1:ff609975e1cd8a58ee862fb3188e8b01b935131d</id>
<content type='text'>
Registers that can be fetched from the info ioctl.

Tested-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: enable SRBM timeout interrupt on EG/NI</title>
<updated>2015-02-25T21:06:08Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-02-18T12:19:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=acc1522a54a3ff4dc250b6e94c55c53c5240e234'/>
<id>urn:sha1:acc1522a54a3ff4dc250b6e94c55c53c5240e234</id>
<content type='text'>
Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>radeon/audio: consolidate audio_set_dto() functions</title>
<updated>2015-01-22T15:42:10Z</updated>
<author>
<name>Slava Grigorev</name>
<email>slava.grigorev@amd.com</email>
</author>
<published>2014-12-05T18:38:31Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=a85d682a6578a3bd02c95afb4ef527fa0897bb69'/>
<id>urn:sha1:a85d682a6578a3bd02c95afb4ef527fa0897bb69</id>
<content type='text'>
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Slava Grigorev &lt;slava.grigorev@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)</title>
<updated>2014-06-02T22:37:33Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2014-05-28T23:14:36Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7b555e068de613b52b068adf3c74f0c774c28365'/>
<id>urn:sha1:7b555e068de613b52b068adf3c74f0c774c28365</id>
<content type='text'>
Program HDMI_CONTROL to send general control packets
for hdmi deep color mode signalling at every video
frame if bpc &gt; 8.

This is only supported on evergreen / DCE-4 and later.

v2: rebase

Signed-off-by: Mario Kleiner &lt;mario.kleiner.de@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/radeon: implement pci config reset for evergreen/cayman (v2)</title>
<updated>2014-01-08T23:42:23Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2013-11-01T20:25:10Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b5470b036e14d063655cc01d22ea5d727042860a'/>
<id>urn:sha1:b5470b036e14d063655cc01d22ea5d727042860a</id>
<content type='text'>
pci config reset is a low level reset that resets
the entire chip from the bus interface.  It can
be more reliable if soft reset fails.

v2: put behind module parameter

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-next</title>
<updated>2013-11-08T06:34:39Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2013-11-08T06:34:39Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=91915260ea5ed9d9b19bfb75d53c989c8ada2ab0'/>
<id>urn:sha1:91915260ea5ed9d9b19bfb75d53c989c8ada2ab0</id>
<content type='text'>
Bit a bit -fixes pull request in the merge window than usual dua to two
feauture-y things:
- Display CRCs are now enabled on all platforms, including the odd DP case
  on gm45/vlv. Since this is a testing-only feature it should ever hurt,
  but I figured it'll help with regression-testing -fixes. So I left it
  in and didn't postpone it to 3.14.
- Display power well refactoring from Imre. Would have caused major pain
  conflict with the bdw stage 1 patches if I'd postpone this to -next.
  It's only an relatively small interface rework, so shouldn't cause pain.
  It's also been in my tree since almost 3 weeks already.

That accounts for about two thirds of the pull, otherwise just bugfixes:
- vlv backlight fix from Jesse/Jani
- vlv vblank timestamp fix from Jesse
- improved edp detection through vbt from Ville (fixes a vlv issue)
- eDP vdd fix from Paulo
- fixes for dvo lvds on i830M
- a few smaller things all over

Note: This contains a backmerge of v3.12. Since the -internal branch
always applied on top of -nightly I need that unified base to merge bdw
patches. So you'll get a conflict with radeon connector props when pulling
this (and nouveau/master will also conflict a bit when Ben doesn't
rebase). The backmerge itself only had conflicts in drm/i915.

There's also a tiny conflict between Jani's backlight fix and your sysfs
lifetime fix in drm-next.

* tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel: (940 commits)
  drm/i915/vlv: use per-pipe backlight controls v2
  drm/i915: make backlight functions take a connector
  drm/i915: move opregion asle request handling to a work queue
  drm/i915/vlv: use PIPE_START_VBLANK interrupts on VLV
  drm/i915: Make intel_dp_is_edp() less specific
  drm/i915: Give names to the VBT child device type bits
  drm/i915/vlv: enable HDA display audio for Valleyview2
  drm/i915/dvo: call -&gt;mode_set callback only when the port is running
  drm/i915: avoid unclaimed registers when capturing the error state
  drm/i915: Enable DP port CRC for the "auto" source on g4x/vlv
  drm/i915: scramble reset support for DP port CRC on vlv
  drm/i915: scramble reset support for DP port CRC on g4x
  drm/i916: add "auto" pipe CRC source
  ...

Conflicts:
	MAINTAINERS
	drivers/gpu/drm/i915/intel_panel.c
	drivers/gpu/drm/nouveau/core/subdev/mc/base.c
	drivers/gpu/drm/radeon/atombios_encoders.c
	drivers/gpu/drm/radeon/radeon_connectors.c
</content>
</entry>
</feed>
