kernel/drivers/gpu/drm/radeon/evergreen.c, branch linux-4.17.y

drm/radeon: fill in rb backend map on evergreen/ni.

2018-01-16T20:35:28Z

This looks to have never gotten filled in, and it seems to trigger a bug in mesa. Reviewed-by: Roland Scheidegger Reported-by: Roland Scheidegger Signed-off-by: Dave Airlie Signed-off-by: Alex Deucher

Backmerge tag 'v4.12-rc7' into drm-next

2017-06-26T22:28:30Z

Linux 4.12-rc7 Needed at least rc6 for drm-misc-next-fixes, may as well go to rc7

drm/radeon: Fix overflow of watermark calcs at > 4k resolutions.

2017-06-14T13:25:58Z

Commit e6b9a6c84b93 ("drm/radeon: Make display watermark calculations more accurate") made watermark calculations more accurate, but not for > 4k resolutions on 32-Bit architectures, as it introduced an integer overflow for those setups and resolutions. Fix this by proper u64 casting and division. Signed-off-by: Mario Kleiner Reported-by: Ben Hutchings Fixes: e6b9a6c84b93 ("drm/radeon: Make display watermark calculations more accurate") Cc: Ben Hutchings Cc: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher

drm/radeon: Cleanup pageflipping IRQ handling for evergreen, si

2017-05-24T22:34:17Z

Same as the previous patch, but for pageflipping now. This also lets us clear up the copy paste for vblank/vline IRQs. Changes since v1: - Preserve the order all registers are written back Acked-by: Christian König Signed-off-by: Lyude Signed-off-by: Alex Deucher

drm/radeon: Cleanup HDMI audio interrupt handling for evergreen

2017-05-24T22:34:07Z

Same as the previous patch, but now for handling HDMI audio interrupts. Changes since v1: - Preserve the order we write back all registers Acked-by: Christian König Signed-off-by: Lyude Signed-off-by: Alex Deucher

drm/radeon: Cleanup display interrupt handling for evergreen, si

2017-05-24T22:33:57Z

The current code here is really, really bad. A huge amount of it looks to be copy pasted, it has some weird hatred of arrays and code sharing, switch cases everywhere for things that really don't need them, and it makes the file seem immensely more complex then it actually is. This is a pain for maintanence, and is vulnerable to more weird irq handling bugs. So, let's start cleaning this up a bit. Modify all of the IRQ handlers for evergreen/si so that they just use for loops. As well, we add a helper function radeon_irq_kms_set_irq_n_enabled(), whose purpose is just to update the state of registers that enable/disable interrupts while printing any changes to the set of enabled interrupts to the kernel log. Note in this commit, since vblank/vline irq acking is intertwined with page flip irq acking, we can't cut out all of the copy paste in evergreen/si_irq_ack() just yet. Changes since v1: - Preserve order we write back all registers Acked-by: Christian König Signed-off-by: Lyude Signed-off-by: Alex Deucher

drm/radeon: Unbreak HPD handling for r600+

2017-05-24T21:39:33Z

We end up reading the interrupt register for HPD5, and then writing it to HPD6 which on systems without anything using HPD5 results in permanently disabling hotplug on one of the display outputs after the first time we acknowledge a hotplug interrupt from the GPU. This code is really bad. But for now, let's just fix this. I will hopefully have a large patch series to refactor all of this soon. Reviewed-by: Christian König Signed-off-by: Lyude Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher

drm/radeon: Unbreak HPD handling for r600+

2017-05-24T20:46:43Z

drm/radeon: Make display watermark calculations more accurate

2017-04-28T21:33:04Z

Avoid big roundoff errors in scanline/hactive durations for high pixel clocks, especially for >= 500 Mhz, and thereby program more accurate display fifo watermarks. This is a port of the corresponding amdgpu patch. Implemented for DCE 4,6,8. Tested on Evergreen/DCE-4 with Radeon HD-5770. Signed-off-by: Mario Kleiner Cc: Alex Deucher Signed-off-by: Alex Deucher

drm/radeon: Avoid overflows/divide-by-zero in latency_watermark calculations.

2017-04-28T21:33:03Z

At dot clocks > approx. 250 Mhz, some of these calcs will overflow and cause miscalculation of latency watermarks, and for some overflows also divide-by-zero driver crash. Make calcs more overflow resistant. This is a direct port of the corresponding patch from amdgpu-kms, copy-paste for cik from dce-8 and si from dce-6, with a slightly simpler variant for evergreen dce-4/5. Only tested on DCE-4 evergreen with a Radeon HD-5770. Signed-off-by: Mario Kleiner Cc: Alex Deucher Signed-off-by: Alex Deucher