kernel/drivers/gpu/drm/pl111/pl111_display.c, branch linux-4.17.y

drm/pl111: Use max memory bandwidth for resolution

2018-03-07T22:14:24Z

We were previously selecting 1024x768 and 32BPP as the default set-up for the PL111 consumers. This does not work on elder systems: the device tree bindings support a property "max-memory-bandwidth" in bytes/second that states that if you exceed this the memory bus will saturate. The result is flickering and unstable images. Parse the "max-memory-bandwidth" and respect it when intializing the driver. On the RealView PB11MP, Versatile and Integrator/CP we get a nice console as default with this code. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20180307215819.15814-1-linus.walleij@linaro.org

drm/pl111: Do not use deprecated drm_driver.{enable|disable)_vblank

2018-02-22T16:58:59Z

Do not use deprecated drm_driver.{enable|disable)_vblank callbacks, but use drm_simple_kms_helpe's pipe callbacks instead. Signed-off-by: Oleksandr Andrushchenko Cc: Eric Anholt Reviewed-by: Eric Anholt Tested-by: Eric Anholt Signed-off-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/1518425574-32671-5-git-send-email-andr2000@gmail.com

drm/pl111: Support variants with broken VBLANK

2018-02-07T08:08:46Z

The early Integrator CLCD synthesized in the Integrator CP and IM-PD1 FPGAs are broken: their vertical and next base interrupts are not functional. Support these variants by simply disabling the use of the vblank interrupt on these variants. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20180206093540.8147-4-linus.walleij@linaro.org

drm/pl111: Support variants with broken clock divider

2018-02-07T08:08:40Z

The early Integrator CLCD synthesized in the Integrator CP and IM-PD1 FPGAs are broken: their clock dividers do not work properly. Support disabling the clock divider and drive the clock directly from the parent under these circumstances. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20180206093540.8147-3-linus.walleij@linaro.org

drm/pl111: Handle the Versatile RGB/BGR565 mode

2018-02-07T08:08:34Z

The ARM Versatile series can do RGB/BGR565 with an external "PLD" (Programmable Logical Device). However the CLCD does not have control bits for this, so it needs to be set into the ordinary 16BPP mode, then the RGB/BGR565 handling of the pixel data is handled by configuring the PLD through the external register. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20180206093540.8147-2-linus.walleij@linaro.org

drm/pl111: Support handling bridge timings

2018-01-12T08:44:50Z

If the bridge has a too strict setup time for the incoming signals, we may not be fast enough and then we need to compensate by outputting the signal on the inverse clock edge so it is for sure stable when the bridge samples it. Since bridges in difference to panels does not expose their connectors, make the connector optional in the display setup code. Acked-by: Laurent Pinchart Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Signed-off-by: Archit Taneja Link: https://patchwork.freedesktop.org/patch/msgid/20180112074854.9560-4-linus.walleij@linaro.org

drm/pl111: Add handling of Versatile platforms

2017-09-10T21:58:42Z

The ARM reference designs in the Versatile family: Integrator, Versatile and RealView can make use of the new DRM driver as well. We just need to create a bit of platform-specific code for them that we isolate to its own file. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20170908124709.4758-7-linus.walleij@linaro.org

drm/pl111: Add optional variant display en/disable callbacks

2017-09-10T21:58:35Z

The silcon and components around the PL111 may require some variants to perform special set-up of the display. Add two callbacks to manage this. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20170908124709.4758-6-linus.walleij@linaro.org

drm/pl111: Insert delay before powering up PL11x

2017-09-10T21:58:29Z

The old codebase has a delay between enabling and powering up the PL11x. According to the manual for PL110, ARM DDI 0161E page 1-5 and the PL111 manual ARM DDI 0293C page 1-6, the power sequence should be such that once Vdd is stable (which we assume it is at boot) LCDEN is enabled first and then CLPOWER should be enabled "after the signals have stabilized" and this is said to be display-dependent. The old codebase uses 20ms. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20170908124709.4758-5-linus.walleij@linaro.org

drm/pl111: Enable PL110 variant

2017-09-10T21:58:16Z

We detect and enable the use of the PL110 variant, an earlier incarnation of PL111. The only real difference is that the control and interrupt enable registers have swapped place. The Versatile AB and Versatile PB have a variant inbetween PL110 and PL111, it is PL110 but they have already swapped the two registers so those two need a bit of special handling. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/20170908124709.4758-4-linus.walleij@linaro.org