kernel/drivers/gpu/drm/omapdrm/dss/pll.c, branch linux-4.17.y

drm: omapdrm: dss: Store the registered plls array in struct dss_device

2018-03-01T07:18:18Z

As part of an effort to remove the usage of global variables in the driver, store the registered plls array in the dss_device structure instead of a global variable. Signed-off-by: Laurent Pinchart Reviewed-by: Sebastian Reichel

drm: omapdrm: Use unsigned int type

2018-03-01T07:09:10Z

The kernel favours 'unsigned int' over plain 'unsigned'. Replace all occurences of the latter by the former. This avoid lots of checkpatch complaints in patches that touch lines where a plain 'unsigned' is used. Signed-off-by: Laurent Pinchart Reviewed-by: Sebastian Reichel Signed-off-by: Tomi Valkeinen

drm: omapdrm: Remove filename from header and fix copyright tag

2017-12-19T09:21:32Z

Having the filename in the header serves little purpose and is often wrong after renames as it is here in several places, just drop it from all omapdrm files. While we are here unify the copyright tags to the TI recommended style. Signed-off-by: Andrew F. Davis

drm/omap: fix i886 work-around

2017-08-23T09:22:09Z

7d267f068a8b4944d52e8b0ae4c8fcc1c1c5c5ba ("drm/omap: work-around for errata i886") changed how the PLL dividers and multipliers are calculated. While the new way should work fine for all the PLLs, it breaks omap5 PLLs. The issues seen are rather odd: seemed that the output clock rate is half of what we asked. It is unclear what's causing there issues. As a work-around this patch adds a "errata_i886" flag, which is set only for DRA7's PLLs, and the PLL setup is done according to that flag. Signed-off-by: Tomi Valkeinen Tested-by: H. Nikolaus Schaller

drm/omap: work-around for errata i886

2017-04-03T09:36:40Z

DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values) says that FPDLink is sensitive to jitter on the vout clock, and that low PLL M and N values result in more jitter than high M and N values. This patch implements a workaround for the problem by changing the PLL setup to search for clocks starting from high M and N values, instead of low values. This should not cause any functional change, and only reduces the jitter. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart

Merge omapdss header refactoring

2016-06-07T09:42:58Z

Merge omapdss public header refactoring, which separates the public header into omapdrm and omapfb parts.

drm/omap: Do not include video/omapdss.h directly in drivers

2016-06-03T13:06:37Z

All drivers to include the omapdrm/dss/omapdss.h header file. This header includes the Signed-off-by: Peter Ujfalusi

drm/omap: add comments for PLL calculations

2016-05-19T17:19:09Z

Add comments showing how the PLL clock rates are calculated. Signed-off-by: Tomi Valkeinen

drm/omap: generalize dss_pll_calc_b()

2016-05-19T17:19:08Z

dss_pll_calc_b() takes HDMI TMDS clock rate as a parameter. To make dss_pll_calc_b() usable for non-HDMI users, change the function to take clkout rate as parameter, and also change the current users of dss_pll_calc_b() to accommodate that. Signed-off-by: Tomi Valkeinen

drm/omap: move HDMI PLL calc function to pll.c

2016-05-19T17:19:08Z

Move hdmi_pll_compute(), used to calculate the config for HDMI PLL, from hdmi_pll.c to pll.c, with the name of dss_pll_calc_b(), to make it available to non-HDMI users. Signed-off-by: Tomi Valkeinen