<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
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<updated>2017-04-06T04:39:03Z</updated>
<entry>
<title>drm/nouveau/secboot: allow to boot multiple falcons</title>
<updated>2017-04-06T04:39:03Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2017-03-29T09:31:09Z</published>
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<id>urn:sha1:598a8148e7208aae64f3c3d33f0ad1a65425965f</id>
<content type='text'>
Change the secboot and msgqueue interfaces to take a mask of falcons to
reset instead of a single falcon. The GP10B firmware interface requires
FECS and GPCCS to be booted in a single firmware command.

For firmwares that only support single falcon boot, it is trivial to
loop over the mask and boot each falcons individually.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: support for different load and unload falcons</title>
<updated>2017-03-07T07:05:13Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2017-01-26T08:18:49Z</published>
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<id>urn:sha1:7defd1daacef6bfae5387e95bcd7b57c9183aaf7</id>
<content type='text'>
On some secure boot instances (e.g. gp10x) the load and unload blobs do
not run on the same falcon. Support this case by introducing a new
member to the ACR structure and making related functions take the falcon
to use as an argument instead of assuming the boot falcon is to be used.

The rule is that the load blob can be run on either the SEC or PMU
falcons, but the unload blob must be always run on PMU.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: support running ACR on SEC</title>
<updated>2017-03-07T07:05:13Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2017-01-26T07:56:45Z</published>
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<id>urn:sha1:48387f0ca5493258add078de7f5520756ddc510a</id>
<content type='text'>
Add support for running the ACR binary on the SEC falcon.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: abstract LS firmware loading functions</title>
<updated>2017-02-17T05:14:32Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-12-14T08:02:45Z</published>
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<id>urn:sha1:9d896f3e41a6093a843ce668c97159367c1e4573</id>
<content type='text'>
The WPR and LSB headers, used to generate the LS blob, may have a
different layout and sizes depending on the driver version they come
from. Abstract them and confine their use to driver-specific code.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: reorganize into more files</title>
<updated>2017-02-17T05:14:31Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-12-14T08:02:39Z</published>
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<id>urn:sha1:72e0642fb4c21632a410c1ff971a63886402b9c9</id>
<content type='text'>
Split the act of building the ACR blob from firmware files from the rest
of the (chip-dependent) secure boot logic. ACR logic is moved into
acr_rxxx.c files, where rxxx corresponds to the compatible release of
the NVIDIA driver. At the moment r352 and r361 are supported since
firmwares have been released for these versions. Some abstractions are
added on top of r352 so r361 can easily be implemented on top of it by
just overriding a few hooks.

This split makes it possible and easy to reuse the same ACR version on
different chips. It also hopefully makes the code much more readable as
the different secure boot logics are separated. As more chips and
firmware versions will be supported, this is a necessity to not get lost
in code that is already quite complex.

This is a big commit, but it essentially moves things around (and split
the nvkm_secboot structure into two, nvkm_secboot and nvkm_acr). Code
semantics should not be affected.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: rename init() hook to oneinit()</title>
<updated>2017-02-17T05:14:31Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-12-14T08:02:35Z</published>
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<id>urn:sha1:808d6efdeb361bd51c1afa2115db0e5f4fe6609d</id>
<content type='text'>
The init() hook is called by the subdev's oneinit(). Rename it
accordingly to avoid confusion about the lifetime of objects allocated
in it.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: remove nvkm_secboot_start()</title>
<updated>2017-02-17T05:14:31Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-12-13T08:11:31Z</published>
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<id>urn:sha1:c8225b54fe1b0d64b7da2c0d1d5b64d316b248f5</id>
<content type='text'>
Since GR has moved to using the falcon library to start the falcons,
this function is not needed anymore.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: use falcon library</title>
<updated>2017-02-17T05:14:31Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-12-13T08:11:27Z</published>
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<id>urn:sha1:d72fb36c45698b9f49a1159eb1a3eb46235d3586</id>
<content type='text'>
Use the falcon library functions in secure boot. This removes a lot of
code and makes the secure boot flow easier to understand as no register
is directly accessed.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: fix functions definitions</title>
<updated>2017-02-17T05:14:31Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-12-13T08:11:26Z</published>
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<id>urn:sha1:236f4747915bbad4cd276654659870b081e882be</id>
<content type='text'>
These functions should use the nvkm_secboot_falcon enum. Fix this.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/secboot: lazy-load firmware and be more resilient</title>
<updated>2016-07-14T01:53:25Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-06-08T08:32:41Z</published>
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<id>urn:sha1:20560a9a3c022ecd960e4657f491d2105da64869</id>
<content type='text'>
Defer the loading of firmware files to the chip-specific part of secure
boot. This allows implementations to retry loading firmware if the first
attempt failed ; for the GM200 implementation, this happens when trying
to reset a falcon, typically in reaction to GR init.

Firmware loading may fail for a variety of reasons, such as the
filesystem where they reside not being ready at init time. This new
behavior allows GR to be initialized the next time we try to use it if
the firmware has become available.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
</feed>
