<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/msm/msm_gpu.h, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y'/>
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<updated>2018-01-10T19:30:03Z</updated>
<entry>
<title>drm/msm: Add devfreq support for the GPU</title>
<updated>2018-01-10T19:30:03Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2018-01-10T17:41:54Z</published>
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<id>urn:sha1:f91c14ab448af4d9d57350301dd9d6b6a7b6128a</id>
<content type='text'>
Add support for devfreq to dynamically control the GPU frequency.
By default try to use the 'simple_ondemand' governor which can
adjust the frequency based on GPU load.

v2: Fix __aeabi_uldivmod issue from the 0 day bot and use
devfreq_recommended_opp() as suggested by Rob.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/gpu: Remove unused bus scaling code</title>
<updated>2018-01-10T13:58:42Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-11-21T19:40:53Z</published>
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<id>urn:sha1:1babd706b455802d17762cb44ecdfcd953bb3dd5</id>
<content type='text'>
Remove the downstream bus scaling code. It isn't needed for for
compatibility with a downstream or vendor kernel. Get it out of the
way to clear space for devfreq support.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: Make the value of RB_CNTL (almost) generic</title>
<updated>2017-10-28T15:01:38Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-10-20T17:07:00Z</published>
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<id>urn:sha1:4d87fc32dfd20ad0d4ffd5204f6e5d41d281e128</id>
<content type='text'>
We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to calculate it once and use
it everywhere.

The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: Support multiple ringbuffers</title>
<updated>2017-10-28T15:01:36Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-10-20T17:06:57Z</published>
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<id>urn:sha1:f97decac5f4c2d862e5b848694e3ffb29fc8acdd</id>
<content type='text'>
Add the infrastructure to support the idea of multiple ringbuffers.
Assign each ringbuffer an id and use that as an index for the various
ring specific operations.

The biggest delta is to support legacy fences. Each fence gets its own
sequence number but the legacy functions expect to use a unique integer.
To handle this we return a unique identifier for each submission but
map it to a specific ring/sequence under the covers. Newer users use
a dma_fence pointer anyway so they don't care about the actual sequence
ID or ring.

The actual mechanics for multiple ringbuffers are very target specific
so this code just allows for the possibility but still only defines
one ringbuffer for each target family.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: Move memptrs to msm_gpu</title>
<updated>2017-10-28T15:01:36Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-10-20T17:06:56Z</published>
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<id>urn:sha1:cd414f3d931687eb1ebeb87533d85537e315f195</id>
<content type='text'>
When we move to multiple ringbuffers we're going to store the data
in the memptrs on a per-ring basis. In order to prepare for that
move the current memptrs from the adreno namespace into msm_gpu.
This is way cleaner and immediately lets us kill off some sub
functions so there is much less cost later when we do move to
per-ring structs.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: Add per-instance submit queues</title>
<updated>2017-10-28T15:01:35Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-10-20T17:06:55Z</published>
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<id>urn:sha1:f7de15450e906ed6586b29bde609a5686cd0d034</id>
<content type='text'>
Currently the behavior of a command stream is provided by the user
application during submission and the application is expected to internally
maintain the settings for each 'context' or 'rendering queue' and specify
the correct ones.

This works okay for simple cases but as applications become more
complex we will want to set context specific flags and do various
permission checks to allow certain contexts to enable additional
privileges.

Add kernel-side submit queues to be analogous to 'contexts' or
'rendering queues' on the application side. Each file descriptor
instance will maintain its own list of queues. Queues cannot be
shared between file descriptors.

For backwards compatibility context id '0' is defined as a default
context specifying no priority and no special flags. This is
intended to be the usual configuration for 99% of applications so
that a garden variety application can function correctly without
creating a queue. Only those applications requiring the specific
benefit of different queues need create one.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: remove address-space id</title>
<updated>2017-06-16T15:16:06Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@gmail.com</email>
</author>
<published>2017-06-13T18:27:45Z</published>
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<id>urn:sha1:8432a903fb97ac3640dbf9281e7c15a673b45747</id>
<content type='text'>
Now that the msm_gem supports an arbitrary number of vma's, we no longer
need to assign an id (index) to each address space.  So rip out the
associated code.

Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: Add a struct to pass configuration to msm_gpu_init()</title>
<updated>2017-06-16T15:16:00Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-05-08T20:35:03Z</published>
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<id>urn:sha1:5770fc7a562e7da37cbf981f352d774c0142d7ba</id>
<content type='text'>
The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: Remove idle function hook</title>
<updated>2017-06-16T15:15:47Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-05-08T20:35:00Z</published>
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<id>urn:sha1:e895c7bd31f5ca7dbd315001cfbdcaee98ee16c4</id>
<content type='text'>
There isn't any generic code that uses -&gt;idle so remove it.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>msm/drm: gpu: Dynamically locate the clocks from the device tree</title>
<updated>2017-04-08T10:59:37Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-03-07T17:02:56Z</published>
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<id>urn:sha1:98db803f6413e6d4bf1f590ea57e9e7dfe1eb32b</id>
<content type='text'>
Instead of using a fixed list of clock names use the clock-names
list in the device tree to discover and get the list of clocks
that we need.

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
</feed>
