kernel/drivers/gpu/drm/msm/mdp, branch linux-4.1.y

drm/msm/mdp5: fix incorrect parameter for msm_framebuffer_iova()

2015-05-21T04:31:45Z

The index of ->planes[] array (3rd parameter) cannot be equal to MAX_PLANE. This looks like a typo that is now fixed. Signed-off-by: Stephane Viau Acked-by: Rob Clark Signed-off-by: Dave Airlie

drm/msm/mdp5: Fix iteration on INTF config array

2015-05-14T15:29:20Z

The current iteration in get_dsi_id_from_intf() is wrong: instead of iterating until hw_cfg->intf.count, we need to iterate until MDP5_INTF_NUM_MAX here. Let's take the example of msm8x16: hw_cfg->intf.count = 1 intfs[0] = INTF_Disabled intfs[1] = INTF_DSI If we stop iterating once i reaches hw_cfg->intf.count (== 1), we will miss the test for intfs[1]. Actually, this hw_cfg->intf.count entry is quite confusing and is not (or *should not be*) used anywhere else; let's remove it. Signed-off-by: Stephane Viau

drm/msm/mdp5: Enable DSI connector in msm drm driver

2015-04-01T23:29:38Z

This change adds the support in mdp5 kms driver for single and dual DSI. Dual DSI case depends on the framework API and sequence change to support dual data path. v1: Initial change v2: Address Rob Clark's comment - Separate command mode encoder to a new file mdp5_cmd_encoder.c - Rebase to not depend on msm_drm_sub_dev change Signed-off-by: Hai Li Signed-off-by: Rob Clark

drm/msm/mdp5: Move *_modeset_init out of construct_encoder function

2015-04-01T23:29:37Z

This change is to make the content in construct_encoder reflect its name. Also, DSI connector may be connected to video mode or command mode encoder, so that 2 different encoders need to be constructed for DSI. Signed-off-by: Hai Li Signed-off-by: Rob Clark

drm/msm/mdp5: Remove CTL flush dummy bits

2015-04-01T23:29:37Z

This TODO can now be removed and replaced by the previous patch "drm/msm/mdp5: Update headers (add CTL flush bits)" Signed-off-by: Stephane Viau Signed-off-by: Rob Clark

drm/msm/mdp5: Update headers (add CTL flush bits)

2015-04-01T23:29:36Z

Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau Signed-off-by: Rob Clark

drm/msm/mdp5: Add hardware configuration for msm8x16

2015-04-01T23:29:36Z

This change adds the hw configuration for msm8x16 chipsets in mdp5_cfg module. Note that only one external display interface is present in this configuration (DSI) but has not been enabled yet. It will be enabled once drm/msm driver supports DSI connectors. v2: add CTL flush register's hardware mask [pointed by Archit] Signed-off-by: Stephane Viau Signed-off-by: Rob Clark

drm/msm/mdp5: Get SMP client list from mdp5_cfg

2015-04-01T23:29:36Z

SMP blocks are configured for specific client IDs (ports). These client IDs can be different from one chip to another for a given pipe. e.g.: DMA0 pipe fetch Y component is connected to: - port #10 for MDP5 v1.3 - port #4 for MDP5 v1.6 In order to be compatible for upcoming versions of MDP5, the client ID list is passed through the MDP5 config module rather than using a list of hard-coded enum values. Signed-off-by: Stephane Viau Signed-off-by: Rob Clark

drm/msm/mdp5: Update headers (remove enum mdp5_client_id)

2015-04-01T23:29:36Z

This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: Stephane Viau Signed-off-by: Rob Clark

drm/msm/mdp5: Separate MDP5 domain from MDSS domain

2015-04-01T23:29:36Z

MDP block is actually contained inside the MDSS block. For some chipsets, the base address of the MDP registers is different from the current (assumed) 0x100 offset. Like CTL and LM blocks, this changes introduce a dynamic offset for the MDP instance, which can be found out at runtime, once the MDSS HW version is read. Signed-off-by: Stephane Viau Signed-off-by: Rob Clark