kernel/drivers/gpu/drm/msm/dsi/phy, branch linux-4.17.y

drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY

2018-04-19T14:08:16Z

Currently the DSI PHY timings are hard-coded for a specific panel for the 10nm PHY. Replace this with the auto PHY timing calculator which can calculate the PHY timings for any panel. Changes in v4: - None Changes in v3: - None Changes in v2: - None Reviewed-by: Sean Paul Reviewed-by: Archit Taneja Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm/dsi: Populate the 10nm PHY funcs

2018-02-20T15:41:21Z

Populate the PHY ops with the downstream driver as reference. There are a couple of TODOs which need to be resolved: - The PHY timings are all hardcoded for now. This needs to be replaced with automatic calculations once we get/understand them. - There are some lane configuration registers which use a new representation between physical and logical lane mappings. For now, we've hardcoced them to follow the default mapping (i.e logical 0 -> phy 0, logical 1 -> phy 1 etc). Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Add skeleton 10nm PHY/PLL code

2018-02-20T15:41:20Z

Add new 10nm DSI PLL/PHY files that will be used on SDM845. Just populate empty pll/phy funcs for now. These will be filled up later. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: check for failure on retrieving pll in dsi manager

2018-02-20T15:41:20Z

Make msm_dsi_pll_init consistently return an error code instead of NULL when pll initialization fails so that later pll retrieval can check against an error code. Add checks for these failures after retrieval of src_pll to avoid invalid pointer dereferences later in msm_dsi_pll_get_clk_provider. Signed-off-by: Lloyd Atkinson Signed-off-by: Rob Clark

drm/msm/dsi: convert to msm_clk_get()

2017-10-28T15:01:33Z

We already have, as a result of upstreaming the gpu bindings, msm_clk_get() which will try to get the clock both without and with a "_clk" suffix. Use this in DSI code so we can drop the "_clk" suffix in bindings while maintaing backwards compatibility. Signed-off-by: Rob Clark Reviewed-by: Sean Paul

drm/msm/dsi: Set up runtime PM for DSI

2017-08-02T11:53:46Z

Call the pm_runtime_get/put API where we need the clocks enabled. The main entry/exit points are 1) enabling/disabling the DSI bridge and 2) Sending commands from the DSI host to the device. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Add PHY/PLL for 8x96

2017-02-06T16:28:45Z

Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL found on 8x96. These are picked up from the downstream driver. The PHY part is similar to the other DSI PHYs. The PLL driver requires some trickery so that one DSI PLL can drive both the DSIs (i.e, dual DSI mode). In the case of dual DSI mode. One DSI instance becomes the clock master, and other the clock slave. The master PLL's output (Byte and Pixel clock) is fed to both the DSI hosts/PHYs. When the DSIs are configured in dual DSI mode, the PHY driver communicates to the PLL driver using msm_dsi_pll_set_usecase() which instance is the master and which one is the slave. When setting rate, the master PLL also configures some of the slave PLL/PHY registers which need to be identical to the master's for correct dual DSI behaviour. There are 2 PLL post dividers that should have ideally been modelled as generic clk_divider clocks, but require some customization for dual DSI. In particular, when the master PLL's post-diviers are set, the slave PLL's post-dividers need to be set too. The clk_ops for these use clk_divider's helper ops and flags internally to prevent redundant code. Cc: Stephen Boyd Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Add new method to calculate 14nm PHY timings

2017-02-06T16:28:45Z

The 14nm DSI PHY on 8x96 (called PHY v2 downstream) requires a different set of calculations for computing D-PHY timing params. Create a timing_calc_v2 func for the newer v2 PHYs. Signed-off-by: Hai Li Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Move PHY operations out of host

2017-02-06T16:28:45Z

Since DSI PHY has been a separate platform device, it should not depend on the resources in host to be functional. This change is to trigger PHY operations in manager, instead of host, so that host and PHY can be completely separated. Signed-off-by: Hai Li Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Pass down use case to PHY

2017-02-06T16:28:45Z

For some new types of DSI PHY, more settings depend on use cases controlled by DSI manager. This change allows DSI manager to setup PHY with a use case. Signed-off-by: Hai Li Signed-off-by: Archit Taneja Signed-off-by: Rob Clark