kernel/drivers/gpu/drm/msm/dsi/phy, branch linux-4.16.y

drm/msm/dsi: convert to msm_clk_get()

2017-10-28T15:01:33Z

We already have, as a result of upstreaming the gpu bindings, msm_clk_get() which will try to get the clock both without and with a "_clk" suffix. Use this in DSI code so we can drop the "_clk" suffix in bindings while maintaing backwards compatibility. Signed-off-by: Rob Clark Reviewed-by: Sean Paul

drm/msm/dsi: Set up runtime PM for DSI

2017-08-02T11:53:46Z

Call the pm_runtime_get/put API where we need the clocks enabled. The main entry/exit points are 1) enabling/disabling the DSI bridge and 2) Sending commands from the DSI host to the device. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Add PHY/PLL for 8x96

2017-02-06T16:28:45Z

Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL found on 8x96. These are picked up from the downstream driver. The PHY part is similar to the other DSI PHYs. The PLL driver requires some trickery so that one DSI PLL can drive both the DSIs (i.e, dual DSI mode). In the case of dual DSI mode. One DSI instance becomes the clock master, and other the clock slave. The master PLL's output (Byte and Pixel clock) is fed to both the DSI hosts/PHYs. When the DSIs are configured in dual DSI mode, the PHY driver communicates to the PLL driver using msm_dsi_pll_set_usecase() which instance is the master and which one is the slave. When setting rate, the master PLL also configures some of the slave PLL/PHY registers which need to be identical to the master's for correct dual DSI behaviour. There are 2 PLL post dividers that should have ideally been modelled as generic clk_divider clocks, but require some customization for dual DSI. In particular, when the master PLL's post-diviers are set, the slave PLL's post-dividers need to be set too. The clk_ops for these use clk_divider's helper ops and flags internally to prevent redundant code. Cc: Stephen Boyd Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Add new method to calculate 14nm PHY timings

2017-02-06T16:28:45Z

The 14nm DSI PHY on 8x96 (called PHY v2 downstream) requires a different set of calculations for computing D-PHY timing params. Create a timing_calc_v2 func for the newer v2 PHYs. Signed-off-by: Hai Li Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Move PHY operations out of host

2017-02-06T16:28:45Z

Since DSI PHY has been a separate platform device, it should not depend on the resources in host to be functional. This change is to trigger PHY operations in manager, instead of host, so that host and PHY can be completely separated. Signed-off-by: Hai Li Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Pass down use case to PHY

2017-02-06T16:28:45Z

For some new types of DSI PHY, more settings depend on use cases controlled by DSI manager. This change allows DSI manager to setup PHY with a use case. Signed-off-by: Hai Li Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Return more timings from PHY to host

2017-02-06T16:28:45Z

The DSI host is required to configure more timings calculated in PHY. By introducing a shared structure, this change allows more timing information passed from PHY to host. Signed-off-by: Hai Li Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Add a PHY op that initializes version specific stuff

2017-02-06T16:28:45Z

Create an init() op for dsi_phy which sets up things specific to a given DSI PHY. The dsi_phy driver probe expects every DSI version to get a "dsi_phy_regulator" mmio base. This isn't the case for 8x96. Creating an init() op will allow us to accommodate such differences. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Don't get DSI index from DT

2016-07-16T14:09:02Z

The DSI host and PHY driver currently expects the DT bindings to provide custom properties "qcom,dsi-host-index" and "qcom,dsi-phy-index" so that the driver can identify which DSI instance it is. The binding isn't acceptable, but the driver still needs to figure out what its instance id. This is now done by storing the mmio starting addresses for each DSI instance in every SoC version in the driver. The driver then identifies the index number by trying to match the stored address with comparing the resource start address we get from DT. We don't have compatible strings for DSI PHY on each SoC, but only the DSI PHY type. We only support one SoC version for each PHY type, so we get away doing the same thing above for the PHY driver. We can revisit this when we support two SoCs with the same DSI PHY. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Fix regulator API abuse

2016-05-08T14:22:17Z

The voltage changing code in this driver is broken and should be removed. The driver sets a single, exact voltage on probe. Unless there is a very good reason for this (which should be documented in comments) constraints like this need to be set via the machine constraints, voltage setting in a driver is expected to be used in cases where the voltage varies at runtime. In addition client drivers should almost never be calling regulator_can_set_voltage(), if the device needs to set a voltage it needs to set the voltage and the regulator core will handle the case where the regulator is fixed voltage. If the driver simply skips setting the voltage if it doesn't have permission then it should just not bother in the first place. Originally authored by Mark Brown Remove the min/max voltage data entries per SoC managed by the driver. These aren't needed as we don't try to set voltages any more. Mention in comments the voltages that each regulator expects. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark