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<title>kernel/drivers/gpu/drm/msm/Kconfig, branch linux-4.16.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.16.y</id>
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<updated>2017-08-01T23:25:51Z</updated>
<entry>
<title>drm/msm: gpu: call qcom_mdt interfaces only for ARCH_QCOM</title>
<updated>2017-08-01T23:25:51Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2017-07-26T15:52:44Z</published>
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<id>urn:sha1:bdab8e8b2bc89dce73b6bcabcd295806ce2e5ef9</id>
<content type='text'>
When compile-testing for something other than ARCH_QCOM,
we run into a link error:

drivers/gpu/drm/msm/adreno/a5xx_gpu.o: In function `a5xx_hw_init':
a5xx_gpu.c:(.text.a5xx_hw_init+0x600): undefined reference to `qcom_mdt_get_size'
a5xx_gpu.c:(.text.a5xx_hw_init+0x93c): undefined reference to `qcom_mdt_load'

There is already an #ifdef that tries to check for CONFIG_QCOM_MDT_LOADER,
but that symbol is only meaningful when building for ARCH_QCOM.

This adds a compile-time check for ARCH_QCOM, and clarifies the
Kconfig select statement so we don't even try it for other targets.

The check for CONFIG_QCOM_MDT_LOADER can then go away, which also
improves compile-time coverage and makes the code a little nicer
to read.

Fixes: 7c65817e6d38 ("drm/msm: gpu: Enable zap shader for A5XX")
Acked-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Acked-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: gpu: Enable zap shader for A5XX</title>
<updated>2017-06-16T15:15:31Z</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2017-05-17T14:45:29Z</published>
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<id>urn:sha1:7c65817e6d38fad8ed4ae8632b3615980a2197b4</id>
<content type='text'>
The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
only render to buffers that are marked as secure and inaccessible
to the kernel and user through a series of hardware protections. In
practice secure mode is used to draw things like a UI on a secure
video frame.

In order to switch out of secure mode the GPU executes a special
shader that clears out the GMEM and other sensitve registers and
then writes a register. Because the kernel can't be trusted the
shader binary is signed and verified and programmed by the
secure world. To do this we need to read the MDT header and the
segments from the firmware location and put them in memory and
present them for approval.

For targets without secure support there is an out: if the
secure world doesn't support secure then there are no hardware
protections and we can freely write the SECVID_TRUST register from
the CPU. We don't have 100% confidence that we can query the
secure capabilities at run time but we have enough calls that
need to go right to give us some confidence that we're at least doing
something useful.

Of course if we guess wrong you trigger a permissions violation
which usually ends up in a system crash but thats a problem
that shows up immediately.

[v2: use child device per Bjorn]
[v3: use generic MDT loader per Bjorn]
[v4: use managed dma functions and ifdefs for the MDT loader]
[v5: Add depends for QCOM_MDT_LOADER]

Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Acked-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
[robclark: fix Kconfig to use select instead of depends + #if IS_ENABLED()]
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: select PM_OPP</title>
<updated>2017-05-27T17:48:24Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@gmail.com</email>
</author>
<published>2017-05-02T16:39:53Z</published>
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<id>urn:sha1:ac20fa0a96c32ff40c8a127dfd58140f1df44a9b</id>
<content type='text'>
Otherwise, if nothing else enabled selects it, dev_pm_opp_of_add_table()
will return -ENOTSUPP.

Fixes: e2af8b6 ("drm/msm: gpu: Use OPP tables if we can")
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Add PHY/PLL for 8x96</title>
<updated>2017-02-06T16:28:45Z</updated>
<author>
<name>Archit Taneja</name>
<email>architt@codeaurora.org</email>
</author>
<published>2017-01-03T14:15:43Z</published>
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<id>urn:sha1:f079f6d999cbf857f899732de680f2b62f245b8c</id>
<content type='text'>
Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL
found on 8x96.

These are picked up from the downstream driver. The PHY part is similar
to the other DSI PHYs. The PLL driver requires some trickery so that
one DSI PLL can drive both the DSIs (i.e, dual DSI mode).

In the case of dual DSI mode. One DSI instance becomes the clock master,
and other the clock slave. The master PLL's output (Byte and Pixel clock)
is fed to both the DSI hosts/PHYs.

When the DSIs are configured in dual DSI mode, the PHY driver communicates
to the PLL driver using msm_dsi_pll_set_usecase() which instance is the
master and which one is the slave. When setting rate, the master PLL also
configures some of the slave PLL/PHY registers which need to be identical
to the master's for correct dual DSI behaviour.

There are 2 PLL post dividers that should have ideally been modelled as
generic clk_divider clocks, but require some customization for dual DSI.
In particular, when the master PLL's post-diviers are set, the slave PLL's
post-dividers need to be set too. The clk_ops for these use clk_divider's
helper ops and flags internally to prevent redundant code.

Cc: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm: add more MMU dependencies</title>
<updated>2017-01-11T16:24:58Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2017-01-11T13:33:35Z</published>
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<id>urn:sha1:f0c379a1cc294fdc6b925f01249477960edc3b90</id>
<content type='text'>
Many DRM drivers only work with an MMU, and after the patch to enable
core DRM support without MMU, we already had one fixup for many of them.
The etnaviv, armada and msm drivers were missed and have the same problem:

warning: (DRM_ETNAVIV) selects IOMMU_SUPPORT which has unmet direct dependencies (MMU)
warning: (DRM_I915 &amp;&amp; DRM_MSM &amp;&amp; DRM_ETNAVIV) selects SHMEM which has unmet direct dependencies (MMU)
drivers/gpu/drm/armada/armada_gem.o: In function `armada_gem_vm_fault':
armada_gem.c:(.text.armada_gem_vm_fault+0x14): undefined reference to `vm_insert_pfn'
arch/arm/mm/dma-mapping.c: In function '__iommu_alloc_remap':
arch/arm/mm/dma-mapping.c:1390:4: error: 'VM_ARM_DMA_CONSISTENT' undeclared (first use in this function)
arch/arm/mm/dma-mapping.c:1456:31: error: 'atomic_pool' undeclared (first use in this function); did you mean 'atomic_xor'?

Fixes: 011cda589938 ("drm: fix compilations issues introduced by "drm: allow to use mmuless SoC"")
Fixes: 62a0d98a188c ("drm: allow to use mmuless SoC")
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20170111133357.3664191-2-arnd@arndb.de
</content>
</entry>
<entry>
<title>drm/msm: submit support for in-fences</title>
<updated>2016-09-15T21:39:49Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@gmail.com</email>
</author>
<published>2016-06-16T20:08:19Z</published>
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<id>urn:sha1:f0a42bb5423a1387e54a2d3451a10d4358b8cfb6</id>
<content type='text'>
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm: msm: Add ASoC generic hdmi audio codec support.</title>
<updated>2016-07-16T14:29:00Z</updated>
<author>
<name>Srinivas Kandagatla</name>
<email>srinivas.kandagatla@linaro.org</email>
</author>
<published>2016-06-10T09:45:56Z</published>
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<id>urn:sha1:f14270161a236235537338d042015988aac354f9</id>
<content type='text'>
This patch adds support to generic audio codec via
ASoC hdmi-codec infrastucture which is merged recently.

Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
[rebased on efc9194]
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: make HDCP support optional</title>
<updated>2016-05-08T14:16:02Z</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@gmail.com</email>
</author>
<published>2016-03-20T14:16:29Z</published>
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<id>urn:sha1:feb46f02c3fa70e6d3e5307cb105cc69c60a3fe3</id>
<content type='text'>
It is already optional at runtime.  But this at least simplifies
backports to kernels without QCOM_SCM.

Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm/dsi: Add support for 28nm PHY on 8960</title>
<updated>2015-12-14T15:40:06Z</updated>
<author>
<name>Archit Taneja</name>
<email>architt@codeaurora.org</email>
</author>
<published>2015-10-14T06:30:34Z</published>
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<id>urn:sha1:225380b3e9b4b82d19de5a161aee169dbc57f353</id>
<content type='text'>
DSI PHY on MSM8960 and APQ8064 is a 28nm PHY that's different from the
supported 28nm LP PHY found in newer chips.

Add support for the new PHY.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/msm: Remove local fbdev emulation Kconfig option</title>
<updated>2015-10-22T19:46:36Z</updated>
<author>
<name>Archit Taneja</name>
<email>architt@codeaurora.org</email>
</author>
<published>2015-07-13T06:42:07Z</published>
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<id>urn:sha1:a9ee34b70e07ce942806eda154e48ea3f754a76f</id>
<content type='text'>
DRM_MSM_FBDEV config is used to enable/disable fbdev emulation for the
msm kms driver.

Replace this with the top level DRM_FBDEV_EMULATION config option where
applicable. This also prevents build breaks caused by undefined
drm_fb_helper_* functions when legacy fbdev support was disabled.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@gmail.com&gt;
</content>
</entry>
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