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<title>kernel/drivers/gpu/drm/mediatek/mtk_drm_ddp.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
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<updated>2017-04-07T16:02:17Z</updated>
<entry>
<title>drm/mediatek: add support for Mediatek SoC MT2701</title>
<updated>2017-04-07T16:02:17Z</updated>
<author>
<name>yt.shen@mediatek.com</name>
<email>yt.shen@mediatek.com</email>
</author>
<published>2017-03-31T11:30:39Z</published>
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<id>urn:sha1:84a5ead18e57e9018d3de0a5388be8f6c2686329</id>
<content type='text'>
This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.

Signed-off-by: YT Shen &lt;yt.shen@mediatek.com&gt;
Acked-by: CK Hu &lt;ck.hu@mediatek.com&gt;
</content>
</entry>
<entry>
<title>drm/mediatek: update display module connections</title>
<updated>2017-04-07T16:02:14Z</updated>
<author>
<name>yt.shen@mediatek.com</name>
<email>yt.shen@mediatek.com</email>
</author>
<published>2017-03-31T11:30:33Z</published>
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<id>urn:sha1:fb2557de27e3e9ced7579c8d97682a0d51d58b3a</id>
<content type='text'>
update connections for OVL, RDMA, BLS, DSI

Signed-off-by: YT Shen &lt;yt.shen@mediatek.com&gt;
Acked-by: CK Hu &lt;ck.hu@mediatek.com&gt;
</content>
</entry>
<entry>
<title>drm/mediatek: add shadow register support</title>
<updated>2017-04-07T16:02:13Z</updated>
<author>
<name>yt.shen@mediatek.com</name>
<email>yt.shen@mediatek.com</email>
</author>
<published>2017-03-31T11:30:31Z</published>
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<id>urn:sha1:9dc84e98a31f64363c32ecae8ec0b9e8cf3ce156</id>
<content type='text'>
We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.

Signed-off-by: YT Shen &lt;yt.shen@mediatek.com&gt;
Acked-by: CK Hu &lt;ck.hu@mediatek.com&gt;
</content>
</entry>
<entry>
<title>drm/mediatek: add *driver_data for different hardware settings</title>
<updated>2017-04-07T16:02:12Z</updated>
<author>
<name>yt.shen@mediatek.com</name>
<email>yt.shen@mediatek.com</email>
</author>
<published>2017-03-31T11:30:30Z</published>
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<id>urn:sha1:c5f228ef6ccddbc3ebc346e2cfb2b11c1762696f</id>
<content type='text'>
There are some hardware settings changed, between MT8173 &amp; MT2701:
DISP_OVL address offset changed, color format definition changed.
DISP_RDMA fifo size changed.
DISP_COLOR offset changed.
MIPI_TX pll setting changed.
And add prefix for mtk_ddp_main &amp; mtk_ddp_ext &amp; mutex_mod.

Signed-off-by: YT Shen &lt;yt.shen@mediatek.com&gt;
Acked-by: CK Hu &lt;ck.hu@mediatek.com&gt;
</content>
</entry>
<entry>
<title>drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.</title>
<updated>2016-05-06T15:47:35Z</updated>
<author>
<name>CK Hu</name>
<email>ck.hu@mediatek.com</email>
</author>
<published>2016-01-04T17:36:34Z</published>
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<id>urn:sha1:119f5173628aa7a0c3cf9db83460d40709e8241d</id>
<content type='text'>
This patch adds an initial DRM driver for the Mediatek MT8173 DISP
subsystem. It currently supports two fixed output streams from the
OVL0/OVL1 sources to the DSI0/DPI0 sinks, respectively.

Signed-off-by: CK Hu &lt;ck.hu@mediatek.com&gt;
Signed-off-by: YT Shen &lt;yt.shen@mediatek.com&gt;
Signed-off-by: Daniel Kurtz &lt;djkurtz@chromium.org&gt;
Signed-off-by: Bibby Hsieh &lt;bibby.hsieh@mediatek.com&gt;
Signed-off-by: Mao Huang &lt;littlecvr@chromium.org&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
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