kernel/drivers/gpu/drm/i915/intel_runtime_pm.c, branch linux-4.1.y

drm/i915: Spelling s/auxilliary/auxiliary/

2015-03-17T21:30:12Z

Signed-off-by: Geert Uytterhoeven Signed-off-by: Daniel Vetter

drm/i915/skl: Restore the DDI translation tables when enabling PW1

2015-03-17T21:30:08Z

I was dumping the DDI translation tables to make sure my patch updating the HDMI entry was doing the right thing when I noticed that the table was showing reset values after DPMS. And indeed, the DDI translation registers are in power well 1 on SKL, and so we're losing their values when shutting down eDP. Calling intel_prepare_ddi() on PW1 enabling re-programs the table. Reviewed-by: Paulo Zanoni Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter

drm/i915: Remove unused condition in hsw_power_well_post_enable()

2015-03-17T21:30:08Z

We don't use this function on gen9, no need for that test here. Reviewed-by: Paulo Zanoni Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter

drm/i915/skl: Restore pipe interrupt registers after power well enabling

2015-03-17T21:30:07Z

The pipe interrupt registers are in the actual pipe power well, so we need to restore them when re-enable the corresponding power well. I've also copied what we do on HSW/BDW for VGA, even if the we haven't enabled unclaimed registers just yet. v2: Don't run skl_power_well_post_enable() if the power well is already enabled (Paulo) Signed-off-by: Damien Lespiau Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter

drm/i915/skl: Mirror what we do on HSW for the power well enable log message

2015-03-17T21:30:07Z

Just to be more consistent with what we do on HSW. Signed-off-by: Damien Lespiau Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter

drm/i915/skl: Introduce enable_requested and is_enabled in the power well code

2015-03-17T21:30:06Z

Just like what we do for HSW/BDW, having those variables makes it a bit easier to parse the code. Suggested-by: Paulo Zanoni Signed-off-by: Damien Lespiau Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter

drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask

2015-03-17T21:30:06Z

While we only need to restore pipe B/C interrupt registers on BDW when enabling the power well, skylake a bit more flexible and we'll also need to restore the pipe A registers as it has its own power well that can be toggled. Reviewed-by: Paulo Zanoni Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter

drm/i915/skl: Implementation of SKL display power well support

2015-02-13T22:28:01Z

This patch implements core logic of SKL display power well. v2: Addressed Imre's comments - Added respective DDIs under power well #1 and #2 - Simplified repetitive code in power well programming v3: Implemented Imre's comments - Further simplified power well programming - Made sure that PW 1 is enabled prior to PW 2 v4: Fix minor conflict with the the cherryview support (Damien) v5: Add the PLL power domain to the always on power well (Damien) v6: Disable BIOS power well (Imre) Use power well data for comparison (Imre) Put the PLL power domain into PW1 as its needed for CDCLK (Satheesh, Damien) v7: Addressed Imre's comments - Lowered the time out to 1ms - Added parantheses in macro - Moved debug message and fixed wait_for interval v8: - Add a WARN() when swiching on an unknown power well (Imre, done by Damien) - Whitespace fixes (spaces instead of tabs) (Damien) v9: (Imre, done by Damien) - Merge the register definitions with this patch - Merge the MISC IO power well in this patch v10: (Imre, done by Damien) - Define the Misc I/O power domains to be the power well 1 ones as Misc I/O needs to be enabled with PW1 - Added Transcoder A and VGA domains to PW 2 - Remove the MISC_IO power domains as well in the the always on domains definition - Move Misc I/O power well at the top of the power well list so it's turned on right after PW1. Reviewed-by: Imre Deak Signed-off-by: Satheeshakrishna M (v3,v6,v7) Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter

drm/i915/skl: Adding power domains for AUX controllers

2015-01-27T08:50:58Z

Adding new power doamins for AUX controllers v2: Added new power domains in power_domain_str per Imre's comment v3: Added AUX power domains to older platforms v4: Rebase on top of POWER_DOMAIN_PLLS. v5: Modified to address review comments from Imre Reviewed-by: Imre Deak Signed-off-by: Satheeshakrishna M Signed-off-by: Damien Lespiau (v3) Signed-off-by: Daniel Vetter Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter

Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queued

2015-01-12T22:07:46Z

Conflicts: drivers/gpu/drm/i915/intel_runtime_pm.c Separate branch so that Takashi can also pull just this refactoring into sound-next. Signed-off-by: Daniel Vetter