<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/i915/intel_fbc.c, branch linux-4.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2015-03-26T12:04:23Z</updated>
<entry>
<title>drm/i915: kill i915.powersave</title>
<updated>2015-03-26T12:04:23Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2015-03-24T19:40:09Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ab585dea120fa20313b1b5a3be2b3d614f094678'/>
<id>urn:sha1:ab585dea120fa20313b1b5a3be2b3d614f094678</id>
<content type='text'>
This flag was being mostly used as a meta flag in some
cases and not covering other cases.

One of the risks is that it was masking some frontbuffer
trackings without disabling PSR.

So, better to kill this at once and avoid umbrella parameters.

Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Acked-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
[danvet: Drop unused out: label to appease gcc.]
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: add frontbuffer tracking to FBC</title>
<updated>2015-03-17T21:29:56Z</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2015-02-13T19:23:46Z</published>
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<id>urn:sha1:dbef0f15b5c83231dacb214dbf9a6dba063ca21c</id>
<content type='text'>
Kill the blt/render tracking we currently have and use the frontbuffer
tracking infrastructure.

Don't enable things by default yet.

v2: (Rodrigo) Fix small conflict on rebase and typo at subject.
v3: (Paulo) Rebase on RENDER_CS change.
v4: (Paulo) Rebase.
v5: (Paulo) Simplify: flushes don't have origin (Daniel).
            Also rebase due to patch order changes.

Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: gen5+ can have FBC with multiple pipes</title>
<updated>2015-02-23T22:59:57Z</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2015-02-13T19:23:43Z</published>
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<id>urn:sha1:e489e38e3f880ec3ff3281c5ceafa3b750600556</id>
<content type='text'>
So allow it.

Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: HSW+ FBC is tied to pipe A</title>
<updated>2015-02-23T22:59:39Z</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2015-02-13T19:23:42Z</published>
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<id>urn:sha1:68b92147d53ad5a6fd59ab066210b988faf5a3c7</id>
<content type='text'>
So add code to consider this case.

v2: Reorder the series, so drop the possible_framebuffer_bits chunk.

Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt; (v1)
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: extract intel_fbc_find_crtc()</title>
<updated>2015-02-23T22:59:28Z</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2015-02-13T19:23:41Z</published>
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<id>urn:sha1:95106753878fc3e60dde6346a71f4d0cb388cb48</id>
<content type='text'>
I want to make this code a little more complicated, so let's extract
the function first.

Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Disable framebuffer compression for i915 driver in VM</title>
<updated>2015-02-13T22:28:24Z</updated>
<author>
<name>Yu Zhang</name>
<email>yu.c.zhang@linux.intel.com</email>
</author>
<published>2015-02-10T11:05:50Z</published>
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<id>urn:sha1:bd49234b6aa37fd32069e506c6997171afd326be</id>
<content type='text'>
Framebuffer compression is disabled when driver detects it's
running in a Intel GVT-g enlightened VM, because FBC is not
emulated and there is no stolen memory for a vGPU.

v2:
take Chris' comments:
        - move the code into intel_update_fbc()

v4:
take Tvrtko's comments:
        - rebase the code into intel_fbc_update()

Signed-off-by: Yu Zhang &lt;yu.c.zhang@linux.intel.com&gt;
Signed-off-by: Jike Song &lt;jike.song@intel.com&gt;
Signed-off-by: Zhiyuan Lv &lt;zhiyuan.lv@intel.com&gt;
Reviewed-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: change dev_priv-&gt;fbc.plane to dev_priv-&gt;fbc.crtc</title>
<updated>2015-02-13T22:28:15Z</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2015-02-09T16:46:29Z</published>
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<id>urn:sha1:e35fef211bab1a69da1b392c3ece906e287ed6e4</id>
<content type='text'>
Since the mapping from CRTCs to planes is fixed, looking at the CRTC
is essentially the same as looking at the plane. Also, the next
patches wil start using the frontbuffer_bits macros, and they take the
pipe as the parameter instead of the plane, and this could differ on
gens 2 and 3.

Another nice thing is that we don't risk accidentally initializing
things to PLANE_A if we don't set the value before it is used for the
first time. But this shouldn't be a problem with the current code.

V2: Rebase.

Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt; (v1)
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: don't keep reassigning FBC_UNSUPPORTED</title>
<updated>2015-02-13T22:28:14Z</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2015-02-09T16:46:28Z</published>
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<id>urn:sha1:104618b3364963d1630297f2b8e0a232c51dc85b</id>
<content type='text'>
This may save a few picoseconds on !HAS_FBC platforms. And it also
satisfies my OCD.

Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: don't try to find crtcs for FBC if it's disabled</title>
<updated>2015-02-13T22:28:14Z</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2015-02-09T16:46:27Z</published>
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<id>urn:sha1:7cc6574600fdd45eb828a884da4eec6daed786f0</id>
<content type='text'>
.. because it would be a waste of time, so move the place where the
check is done. Also, with this we won't risk printing "more than one
pipe active, disabling compression" or "no output, disabling" when FBC
is actually disabled.

This patch also represents a small behavior difference when using
i915.powersave=0: it is now exactly the same as i915.enable_fbc=0 on
this part of the code.

V2: Rebase.

Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt; (v1)
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915/fbc: fix the check for already reserved fbc size</title>
<updated>2015-02-13T22:28:03Z</updated>
<author>
<name>Jani Nikula</name>
<email>jani.nikula@intel.com</email>
</author>
<published>2015-02-05T10:04:27Z</published>
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<id>urn:sha1:60ee5cd24cf1c39d4c7bab7b428a08386a93fe9f</id>
<content type='text'>
The check for previously reserved stolen space size for FBC in
i915_gem_stolen_setup_compression() did not take the compression
threshold into account. Fix this by storing and comparing to
uncompressed size instead.

The bug has been introduced in

commit 5e59f7175f96550ede91f58d267d2b551cb6fbba
Author: Ben Widawsky &lt;benjamin.widawsky@intel.com&gt;
Date:   Mon Jun 30 10:41:24 2014 -0700

    drm/i915: Try harder to get FBC

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88975
Suggested-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Ben Widawsky &lt;benjamin.widawsky@intel.com&gt;
Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
Reviewed-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
</feed>
