drm/i915/cnl: Simplify dco_fraction calculation.

2017-11-16T17:45:39Z

I confess I never fully understood that previous calculation, so this is not a "fix". But let's simplify this math so poor brains like mine can read and make some sense of it in the future. v2: Don't follow the spec since that gives invalid values and it is also confusing. This Ville's version is much simpler. v3: Use u64 cast instead of declaring a u64 dco. (Ville). Cc: Ville Syrjälä Cc: Mika Kahola Cc: Manasi Navare Cc: James Ausmus Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171115184257.8633-1-rodrigo.vivi@intel.com

drm/i915/cnl: Don't blindly replace qdiv.

2017-11-16T17:45:16Z

Accordingly to spec "If Kdiv != 2, then Qdiv must be 1." but we already handle qdiv values properly and this case here should be spurious. But instead of blindly replacing let's warn loudly instead. Because it means something was really wrong on initial setup. Cc: Mika Kahola Cc: Manasi Navare Cc: James Ausmus Signed-off-by: Rodrigo Vivi Reviewed-by: Manasi Navare Link: https://patchwork.freedesktop.org/patch/msgid/20171114194759.24541-6-rodrigo.vivi@intel.com

drm/i915/cnl: Fix wrpll math for higher freqs.

2017-11-16T17:44:48Z

Spec describe all values in MHz. We handle our clocks in KHz. This includes the best_dco_centrality that was forgot in the same unity as spec. Consequently we couldn't get a good divider for high frequenies. Hence HDMI 2.0 wasn't working. Spec tells 999999 for initial best_dco_centrality meaning the max value in MHz. Since we convert dco from MHz to KHz we also need to convert this initial best_doc_centrality to 999999000 or 999999999 or even better, to the max that its variable allow. This patch also replaces the use of "* KHz(1)" with the values directly on KHz to avoid future confusion. v2: Use U32_MAX instead of random 99999 as spec tells. (Ville). Cc: Ville Syrjälä Cc: Shashank Sharma Cc: Mika Kahola Cc: Manasi Navare Cc: James Ausmus Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171114234223.10600-1-rodrigo.vivi@intel.com

drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.

2017-11-16T17:44:18Z

- 64 bits is not needed for afe_clock now we don't convert that to Hz. - 16 bits is not enough for all dco stuff. - unsigned is not relevant/needed for all divisors values. Cc: Mika Kahola Cc: Manasi Navare Cc: James Ausmus Signed-off-by: Rodrigo Vivi Reviewed-by: Manasi Navare

drm/i915/cnl: Remove useless conversion.

2017-11-16T17:44:05Z

No functional change. Just starting the wrpll fixes with a clean-up to make units a bit more clear. Cc: Mika Kahola Cc: Manasi Navare Cc: James Ausmus Signed-off-by: Rodrigo Vivi Reviewed-by: Manasi Navare Link: https://patchwork.freedesktop.org/patch/msgid/20171114194759.24541-3-rodrigo.vivi@intel.com

drm/i915/cnl: Remove spurious central_freq.

2017-11-16T17:43:37Z

"Display software must leave this field at the default value. It no longer needs to be configured as part of PLL programming." We respect this already and we are setting up the default one line below: "DPLL_CFGCR1_CENTRAL_FREQ". Also we don't touch anywhere else this central_freq for cnl. So let's remove from the final write. No functional change. Only a clean-up patch. Cc: Manasi Navare Cc: Mika Kahola Cc: James Ausmus Signed-off-by: Rodrigo Vivi Reviewed-by: Manasi Navare Link: https://patchwork.freedesktop.org/patch/msgid/20171114194759.24541-2-rodrigo.vivi@intel.com

drm/i915: Replace dig_port->port with encoder port for BXT DPLL selection

2017-11-09T18:06:06Z

Replace dig_port->port with encoder->port in the BXT DPLL selection. We can do this because both the master encoder and the fake MST encoders have the same encoder->port value, whereas using dig_port->port only worked for the master encoder since the fake encoders were't derived from intel_digital_port. This eliminates the DP MST special case. Do this by hand because spatch is having problems with the control flow due to the dig_port assignment happening in two different branches. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171031205123.13123-8-ville.syrjala@linux.intel.com Acked-by: Jani Nikula Reviewed-by: Dhinakaran Pandiyan

drm/i915: Start using output_types for DPLL selection

2017-10-27T15:45:36Z

encoder->type is not realiable for DP/HDMI so let's switch the DPLL selection over to using output_types. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20171019133721.11794-4-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst

drm/i915: Adjust system agent voltage on CNL if required by DDI ports

2017-10-25T10:40:52Z

On CNL we may need to bump up the system agent voltage not only due to CDCLK but also when driving DDI port with a sufficiently high clock. To that end start tracking the minimum acceptable voltage for each crtc. We do the tracking via crtcs because we don't have any kind of encoder state. Also there's no downside to doing it this way, and it matches how we track cdclk requirements on account of pixel rate. v2: Allow disabled crtcs to use the min voltage Add IS_CNL check to intel_ddi_compute_min_voltage() since we're using CNL specific values there s/intel_compute_min_voltage/cnl_compute_min_voltage/ since the function makes hw specific assumptions about the voltage values v3: Drop the test hack leftovers from skl_modeset_calc_cdclk() v4: s/voltage/voltage_level/ (Rodrigo) Replace DPLL DVFS FIXMEs with an explanation why we don't do anything there (Rodrigo) Cc: Mika Kahola Cc: Manasi Navare Cc: Rodrigo Vivi Signed-off-by: Ville Syrjälä Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-9-ville.syrjala@linux.intel.com

drm/i915/cnl: Fix PLL initialization for HDMI.

2017-10-16T23:50:05Z

HDMI Mode selection on CNL is on CFGCR0 for that PLL, not on in a global CTRL1 as it was on SKL. The original patch addressed this difference, but leaving behind this single entry here. So we were checking the wrong bits during the PLL initialization and consequently avoiding the CFGCR1 setup during HDMI initialization. Luckly when only HDMI was in use BIOS had already setup this for us. But the dual display with hot plug were messed up. Fixes: a927c927de34 ("drm/i915/cnl: Initialize PLLs") Cc: Paulo Zanoni Cc: Manasi Navare Cc: Kahola, Mika Signed-off-by: Rodrigo Vivi Reviewed-by: James Ausmus Reviewed-by: Manasi Navare Link: https://patchwork.freedesktop.org/patch/msgid/20171003220859.21352-3-rodrigo.vivi@intel.com

kernel/drivers/gpu/drm/i915/intel_dpll_mgr.c, branch linux-4.17.y