kernel/drivers/gpu/drm/i915/intel_device_info.h, branch linux-4.17.y

drm/i915/debugfs: add rcs topology entry

2018-03-08T10:06:21Z

While the end goal is to make this information available to userspace through a new ioctl, there is no reason we can't display it in a human readable fashion through debugfs. slice0: 3 subslice(s) (0x7): subslice0: 8 EUs (0xff) subslice1: 8 EUs (0xff) subslice2: 8 EUs (0xff) subslice3: 0 EUs (0x0) slice1: 3 subslice(s) (0x7): subslice0: 8 EUs (0xff) subslice1: 8 EUs (0xff) subslice2: 8 EUs (0xff) subslice3: 0 EUs (0x0) slice2: 3 subslice(s) (0x7): subslice0: 8 EUs (0xff) subslice1: 8 EUs (0xff) subslice2: 8 EUs (0xff) subslice3: 0 EUs (0x0) v2: Reformat debugfs printing (Tvrtko) Use the new EU mask helper (Tvrtko) v3: Move printing code to intel_device_info.c to be shared with error state (Michal) v4: Bump u8 to u16 when using sseu_get_eus() (Lionel) Suggested-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin Acked-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20180306122857.27317-4-lionel.g.landwerlin@intel.com

drm/i915: store all subslice masks

2018-03-08T10:06:20Z

Up to now, subslice mask was assumed to be uniform across slices. But starting with Cannonlake, slices can be asymmetric (for example slice0 has different number of subslices as slice1+). This change stores all subslices masks for all slices rather than having a single mask that applies to all slices. v2: Rework how we store total numbers in sseu_dev_info (Tvrtko) Fix CHV eu masks, was reading disabled as enabled (Tvrtko) Readability changes (Tvrtko) Add EU index helper (Tvrtko) v3: Turn ALIGN(v, 8) / 8 into DIV_ROUND_UP(v, BITS_PER_BYTE) (Tvrtko) Reuse sseu_eu_idx() for setting eu_mask on CHV (Tvrtko) Reformat debug prints for subslices (Tvrtko) v4: Change eu_mask helper into sseu_set_eus() (Tvrtko) v5: With Haswell reporting masks & counts, bump sseu_*_eus() functions to use u16 (Lionel) v6: Fix sseu_get_eus() for > 8 EUs per subslice (Lionel) v7: Change debugfs enabels for number of subslices per slice, will need a small igt/pm_sseu change (Lionel) Drop subslice_total field from sseu_dev_info, rely on sseu_subslice_total() to recompute the value instead (Lionel) v8: Remove unused function compute_subslice_total() (Lionel) Signed-off-by: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin Acked-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20180306122857.27317-2-lionel.g.landwerlin@intel.com

drm/i915/icl: Enhanced execution list support

2018-03-07T13:07:31Z

Enhanced Execlists is an upgraded version of execlists which supports up to 8 ports. The lrcs to be submitted are written to a submit queue (the ExecLists Submission Queue - ELSQ), which is then loaded on the HW. When writing to the ELSP register, the lrcs are written cyclically in the queue from position 0 to position 7. Alternatively, it is possible to write directly in the individual positions of the queue using the ELSQC registers. To be able to re-use all the existing code we're using the latter method and we're currently limiting ourself to only using 2 elements. v2: Rebase. v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio). v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio) v5: Reword commit, rename regs to be closer to specs, turn off preemption (Daniele), reuse engine->execlists.elsp (Chris) v6: use has_logical_ring_elsq to differentiate the new paths v7: add preemption support, rename els to submit_reg (Chris) v8: save the ctrl register inside the execlists struct, drop CSB handling updates (superseded by preempt_complete_status) (Chris) v9: s/drm_i915_gem_request/i915_request (Mika) v10: resolved conflict in inject_preempt_context (Mika) Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Thomas Daniel Signed-off-by: Rodrigo Vivi Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20180302161501.28594-4-mika.kuoppala@linux.intel.com

drm/i915/icl: Prepare for more rings

2018-03-01T12:13:47Z

Gen11 will add more VCS and VECS rings so prepare the infrastructure to support that. Bspec: 7021 v2: Rebase. v3: Rebase. v4: Rebase. v5: Rebase. v6: - Update for POR changes. (Daniele Ceraolo Spurio) - Add provisional guc engine ids - to be checked and confirmed. v7: - Rebased. - Added the new ring masks. - Added the new HW ids. v8: - Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal) v9: increase MAX_ENGINE_INSTANCE to 3 Cc: Michal Wajdeczko Signed-off-by: Tvrtko Ursulin Signed-off-by: Rodrigo Vivi Signed-off-by: Oscar Mateo Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Oscar Mateo Signed-off-by: Mika Kuoppala Link: https://patchwork.freedesktop.org/patch/msgid/20180228101153.7224-1-mika.kuoppala@linux.intel.com

drm/i915: Move page sizes out of the 8-bit sandwich

2018-02-22T14:14:23Z

Slightly smaller code and a bit more logical layout. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20180222111658.4999-1-tvrtko.ursulin@linux.intel.com

drm/i915: Move the scheduler feature bits into the purview of the engines

2018-02-08T07:30:11Z

Rather than having the high level ioctl interface guess the underlying implementation details, having the implementation declare what capabilities it exports. We define an intel_driver_caps, similar to the intel_device_info, which instead of trying to describe the HW gives details on what the driver itself supports. This is then populated by the engine backend for the new scheduler capability field for use elsewhere. v2: Use caps.scheduler for validating CONTEXT_PARAM_SET_PRIORITY (Mika) One less assumption of engine[RCS] \o/ Signed-off-by: Chris Wilson Cc: Tomasz Lis Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Cc: Michal Wajdeczko Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala Reviewed-by: Tomasz Lis Link: https://patchwork.freedesktop.org/patch/msgid/20180207210544.26351-2-chris@chris-wilson.co.uk Reviewed-by: Michel Thierry

drm/i915/icl: Add initial Icelake definitions.

2018-01-19T19:52:59Z

Icelake is an Intel® Processor containing an Intel® Graphics Controller. This is just an initial Icelake definition. PCI IDs, Icelake support and new features coming in following patches. v2: Add .ddb_size and .has_guc (Michal Wajdeczko). v3: Add the ICL_FEATURES macro (Kelvin Gardiner). v4 (from Paulo): Add missing __initconst (Paulo) and say "graphics controller" instead of something that looks like an official marketing name but isn't (Chris). Reviewed-by: Rodrigo Vivi Reviewed-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni Link: https://patchwork.freedesktop.org/patch/msgid/20180111180010.24357-3-paulo.r.zanoni@intel.com

drm/i915: Add pretty printer for runtime part of intel_device_info

2017-12-22T09:19:49Z

During initialization of the runtime part of the intel_device_info we are dumping that part using DRM_DEBUG_DRIVER mechanism. As we already have pretty printer for const part of the info, make similar function for the runtime part and use it separately. v2: add runtime dump to debugfs (Chris) Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Rodrigo Vivi Cc: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20171221185334.17396-7-michal.wajdeczko@intel.com Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171221215735.30314-6-chris@chris-wilson.co.uk

drm/i915: Update intel_device_info_runtime_init() parameter

2017-12-22T09:19:49Z

As we try to follow object-verb pattern in our functions, update intel_device_info_runtime_init() parameter from dev_priv to info. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Rodrigo Vivi Cc: Joonas Lahtinen Reviewed-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171221185334.17396-6-michal.wajdeczko@intel.com Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171221215735.30314-5-chris@chris-wilson.co.uk

drm/i915: Move intel_device_info definitions to its own header

2017-12-22T09:19:48Z

We already keep intel_device_info functions in dedicated file. Add matching header file and move related definitions there. v2: add gen boundaries (Chris) Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Rodrigo Vivi Cc: Joonas Lahtinen Reviewed-by: Chris Wilson Acked-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20171221185334.17396-5-michal.wajdeczko@intel.com Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20171221215735.30314-4-chris@chris-wilson.co.uk