<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/i915/i915_gpu_error.c, branch linux-4.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2015-03-25T17:23:44Z</updated>
<entry>
<title>drm/i915: Add fault address to error state for gen8 and gen9</title>
<updated>2015-03-25T17:23:44Z</updated>
<author>
<name>Mika Kuoppala</name>
<email>mika.kuoppala@linux.intel.com</email>
</author>
<published>2015-03-24T12:54:19Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=6c826f349587f6c897da9bd224912ca1aee3d9ea'/>
<id>urn:sha1:6c826f349587f6c897da9bd224912ca1aee3d9ea</id>
<content type='text'>
The faulting virtual address is &gt;32bits and has been moved
to different registers. Add to error state and output upper
register first, in the same line for easy reconstruction of
the fault address.

v2: correct gen masking (Michel)
v3: s/TBL/TLB (Ville)

Signed-off-by: Mika Kuoppala &lt;mika.kuoppala@intel.com&gt;
Reviewed-by: Michel Thierry &lt;michel.thierry@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Do not leak objects after capturing error state</title>
<updated>2015-03-20T14:46:46Z</updated>
<author>
<name>Michel Thierry</name>
<email>michel.thierry@intel.com</email>
</author>
<published>2015-03-20T09:41:03Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=0b37a9a9ebdf47dc9d5290a1c69bd944dde5cc15'/>
<id>urn:sha1:0b37a9a9ebdf47dc9d5290a1c69bd944dde5cc15</id>
<content type='text'>
While running kmemleak chasing a different memleak, I saw that the
capture_error_state function was leaking some objects, for example:

unreferenced object 0xffff8800a9b72148 (size 8192):
  comm "kworker/u16:0", pid 1499, jiffies 4295201243 (age 990.096s)
  hex dump (first 32 bytes):
    00 00 04 00 00 00 00 00 5d f4 ff ff 00 00 00 00  ........].......
    00 30 b0 01 00 00 00 00 37 00 00 00 00 00 00 00  .0......7.......
  backtrace:
    [&lt;ffffffff811e5ae4&gt;] create_object+0x104/0x2c0
    [&lt;ffffffff8178f50a&gt;] kmemleak_alloc+0x7a/0xc0
    [&lt;ffffffff811cde4b&gt;] __kmalloc+0xeb/0x220
    [&lt;ffffffffa038f1d9&gt;] kcalloc.constprop.12+0x2d/0x2f [i915]
    [&lt;ffffffffa0316064&gt;] i915_capture_error_state+0x3f4/0x1660 [i915]
    [&lt;ffffffffa03207df&gt;] i915_handle_error+0x7f/0x660 [i915]
    [&lt;ffffffffa03210f7&gt;] i915_hangcheck_elapsed+0x2e7/0x470 [i915]
    [&lt;ffffffff8108d574&gt;] process_one_work+0x144/0x490
    [&lt;ffffffff8108dfbd&gt;] worker_thread+0x11d/0x530
    [&lt;ffffffff81094079&gt;] kthread+0xc9/0xe0
    [&lt;ffffffff817a2398&gt;] ret_from_fork+0x58/0x90
    [&lt;ffffffffffffffff&gt;] 0xffffffffffffffff

The following objects are allocated in i915_gem_capture_buffers, but not
released in i915_error_state_free:
  - error-&gt;active_bo_count
  - error-&gt;pinned_bo
  - error-&gt;pinned_bo_count
  - error-&gt;active_bo[vm_count] (allocated in i915_gem_capture_vm).

The leaks were introduced by
commit 95f5301dd880da2dea2c9a9c29750064536d426a
Author: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Date:   Wed Jul 31 17:00:15 2013 -0700

    drm/i915: Update error capture for VMs

v2: Reuse iterator and add culprit commit details (Chris)

Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Michel Thierry &lt;michel.thierry@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Add process identifier to requests</title>
<updated>2015-02-13T22:28:37Z</updated>
<author>
<name>Mika Kuoppala</name>
<email>mika.kuoppala@linux.intel.com</email>
</author>
<published>2015-02-12T08:26:02Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=071c92de1d24f36a217fb8264df27998c8c73df6'/>
<id>urn:sha1:071c92de1d24f36a217fb8264df27998c8c73df6</id>
<content type='text'>
We use the pid of the process which opened our device when
we track which was the culprit of the gpu hang. But as that
file descriptor might get inherited, we might blame the
wrong process when we record the error state.

Track process identifiers in requests to always find
the correct offender.

v2: Track only user processes (Chris)

Cc: Kenneth Graunke &lt;kenneth@whitecape.org&gt;
Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Mika Kuoppala &lt;mika.kuoppala@intel.com&gt;
[danvet: drop NULL check before put_pid as suggested by Chris.]
Reviewed-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Removed duplicate members from submit_request</title>
<updated>2015-01-27T08:50:52Z</updated>
<author>
<name>Nick Hoath</name>
<email>nicholas.hoath@intel.com</email>
</author>
<published>2015-01-15T13:10:37Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=72f95afa5faaf899f7344879b6ccd5f0cb271b28'/>
<id>urn:sha1:72f95afa5faaf899f7344879b6ccd5f0cb271b28</id>
<content type='text'>
Where there were duplicate variables for the tail, context and ring (engine)
in the gem request and the execlist queue item, use the one from the request
and remove the duplicate from the execlist queue item.

Issue: VIZ-4274

v1: Rebase
v2: Fixed build issues. Keep separate postfix &amp; tail pointers as these are
used in different ways. Reinserted missing full tail pointer update.

Signed-off-by: Nick Hoath &lt;nicholas.hoath@intel.com&gt;
Reviewed-by: Thomas Daniel &lt;thomas.daniel@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Organize INSTDONE report for future.</title>
<updated>2014-12-17T17:18:43Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2014-12-03T12:55:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=563f94f6faefe8cb497245a3511b272587ebd85b'/>
<id>urn:sha1:563f94f6faefe8cb497245a3511b272587ebd85b</id>
<content type='text'>
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.

Cc: Damien Lespiau &lt;damien.lespiau@intel.com&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Organize PDP regs report for future.</title>
<updated>2014-12-17T17:18:34Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2014-12-03T12:55:27Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=74745b093889aee5887e327b0108d56ba3ab9629'/>
<id>urn:sha1:74745b093889aee5887e327b0108d56ba3ab9629</id>
<content type='text'>
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.

Cc: Damien Lespiau &lt;damien.lespiau@intel.com&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Organize Fence registers for future enablement.</title>
<updated>2014-12-17T17:17:54Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2014-12-04T14:48:10Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ce38ab05931484e72f776d04bb5d27c82744dd24'/>
<id>urn:sha1:ce38ab05931484e72f776d04bb5d27c82744dd24</id>
<content type='text'>
Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.

v2: Jani pointed out I was missing reg_830 for some gen3 platforms. So let's make
    this platforms subcases of Gen checks.

Cc: Jani Nikula &lt;jani.nikula@intel.com&gt;
Cc: Damien Lespiau &lt;damien.lespiau@intel.com&gt;
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Infrastructure for supporting different GGTT views per object</title>
<updated>2014-12-15T10:25:04Z</updated>
<author>
<name>Tvrtko Ursulin</name>
<email>tvrtko.ursulin@intel.com</email>
</author>
<published>2014-12-10T17:27:58Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=fe14d5f4e5468c5b80a24f1a64abcbe116143670'/>
<id>urn:sha1:fe14d5f4e5468c5b80a24f1a64abcbe116143670</id>
<content type='text'>
Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
to map objects into the same address space multiple times.

Added a GGTT view concept and linked it with the VMA to distinguish between
multiple instances per address space.

New objects and GEM functions which do not take this new view as a parameter
assume the default of zero (I915_GGTT_VIEW_NORMAL) which preserves the
previous behaviour.

This now means that objects can have multiple VMA entries so the code which
assumed there will only be one also had to be modified.

Alternative GGTT views are supposed to borrow DMA addresses from obj-&gt;pages
which is DMA mapped on first VMA instantiation and unmapped on the last one
going away.

v2:
    * Removed per view special casing in i915_gem_ggtt_prepare /
      finish_object in favour of creating and destroying DMA mappings
      on first VMA instantiation and last VMA destruction. (Daniel Vetter)
    * Simplified i915_vma_unbind which does not need to count the GGTT views.
      (Daniel Vetter)
    * Also moved obj-&gt;map_and_fenceable reset under the same check.
    * Checkpatch cleanups.

v3:
    * Only retire objects once the last VMA is unbound.

v4:
    * Keep scatter-gather table for alternative views persistent for the
      lifetime of the VMA.
    * Propagate binding errors to callers and handle appropriately.

v5:
    * Explicitly look for normal GGTT view in i915_gem_obj_bound to align
      usage in i915_gem_object_ggtt_unpin. (Michel Thierry)
    * Change to single if statement in i915_gem_obj_to_ggtt. (Michel Thierry)
    * Removed stray semi-colon in i915_gem_object_set_cache_level.

For: VIZ-4544
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Cc: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Reviewed-by: Michel Thierry &lt;michel.thierry@intel.com&gt;
[danvet: Drop hunk from i915_gem_shrink since it's just prettification
but upsets a __must_check warning.]
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Remove the now redundant 'obj-&gt;ring'</title>
<updated>2014-12-03T08:35:23Z</updated>
<author>
<name>John Harrison</name>
<email>John.C.Harrison@Intel.com</email>
</author>
<published>2014-11-24T18:49:43Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=41c5241555d762810f975d5d9d70143aa93834cd'/>
<id>urn:sha1:41c5241555d762810f975d5d9d70143aa93834cd</id>
<content type='text'>
The ring member of the object structure was always updated with the
last_read_seqno member. Thus with the conversion to last_read_req, obj-&gt;ring is
now a direct copy of obj-&gt;last_read_req-&gt;ring. This makes it somewhat redundant
and potentially misleading (especially as there was no comment to explain its
purpose).

This checkin removes the redundant field. Many uses were simply testing for
non-null to see if the object is active on the GPU. Some of these have been
converted to check 'obj-&gt;active' instead. Others (where the last_read_req is
about to be used anyway) have been changed to check obj-&gt;last_read_req. The rest
simply pull the ring out from the request structure and proceed as before.

For: VIZ-4377
Signed-off-by: John Harrison &lt;John.C.Harrison@Intel.com&gt;
Reviewed-by: Thomas Daniel &lt;Thomas.Daniel@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Replace last_[rwf]_seqno with last_[rwf]_req</title>
<updated>2014-12-03T08:35:14Z</updated>
<author>
<name>John Harrison</name>
<email>John.C.Harrison@Intel.com</email>
</author>
<published>2014-11-24T18:49:26Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=97b2a6a10a1aef6f32832fcbc9d6a27650354904'/>
<id>urn:sha1:97b2a6a10a1aef6f32832fcbc9d6a27650354904</id>
<content type='text'>
The object structure contains the last read, write and fenced seqno values for
use in syncrhonisation operations. These have now been replaced with their
request structure counterparts.

Note that to ensure that objects do not end up with dangling pointers, the
assignments of last_*_req include reference count updates. Thus a request cannot
be freed if an object is still hanging on to it for any reason.

v2: Corrected 'last_rendering_' to 'last_read_' in a number of comments that did
not get updated when 'last_rendering_seqno' became 'last_read|write_seqno'
several millenia ago.

For: VIZ-4377
Signed-off-by: John Harrison &lt;John.C.Harrison@Intel.com&gt;
Reviewed-by: Thomas Daniel &lt;Thomas.Daniel@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
</feed>
