drm/i915: Split obj->cache_coherent to track r/w

2017-08-15T14:46:57Z

Another month, another story in the cache coherency saga. This time, we come to the realisation that i915_gem_object_is_coherent() has been reporting whether we can read from the target without requiring a cache invalidate; but we were using it in places for testing whether we could write into the object without requiring a cache flush. So split the tracking into two, one to decide before reads, one after writes. See commit e27ab73d17ef ("drm/i915: Mark CPU cache as dirty on every transition for CPU writes") for the previous entry in this saga. v2: Be verbose v3: Remove unused function (i915_gem_object_is_coherent) v4: Fix inverted coherency check prior to execbuf (from v2) v5: Add comment for nasty code where we are optimising on gcc's behalf. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101109 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101555 Testcase: igt/kms_mmap_write_crc Testcase: igt/kms_pwrite_crc Signed-off-by: Chris Wilson Cc: Maarten Lankhorst Cc: Dongwon Kim Cc: Matt Roper Cc: Joonas Lahtinen Cc: Mika Kuoppala Tested-by: Maarten Lankhorst Acked-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20170811111116.10373-1-chris@chris-wilson.co.uk Reviewed-by: Joonas Lahtinen

kernel/drivers/gpu/drm/i915/i915_gem_object.c, branch linux-4.17.y

drm/i915: Split obj->cache_coherent to track r/w