<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/i915/i915_cmd_parser.c, branch linux-4.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.1.y'/>
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<updated>2015-03-17T21:30:31Z</updated>
<entry>
<title>drm/i915: Fix vmap_batch page iterator overrun</title>
<updated>2015-03-17T21:30:31Z</updated>
<author>
<name>Mika Kuoppala</name>
<email>mika.kuoppala@linux.intel.com</email>
</author>
<published>2015-03-13T13:21:53Z</published>
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<id>urn:sha1:72c5ba9562147d3fc2d22cd44c30bd136cd4a1ac</id>
<content type='text'>
vmap_batch() calculates amount of needed pages for the mapping
we are going to create. And it uses this page count as an
argument for the for_each_sg_pages() macro. The macro takes the number
of sg list entities as an argument, not the page count. So we ended
up iterating through all the pages on the mapped object, corrupting
memory past the smaller pages[] array.

Fix this by bailing out when we have enough pages.

This regression has been introduced in

commit 17cabf571e50677d980e9ab2a43c5f11213003ae
Author: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Date:   Wed Jan 14 11:20:57 2015 +0000

    drm/i915: Trim the command parser allocations

Cc: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Mika Kuoppala &lt;mika.kuoppala@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Trim the command parser allocations</title>
<updated>2015-02-23T16:07:40Z</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2015-01-14T11:20:57Z</published>
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<id>urn:sha1:17cabf571e50677d980e9ab2a43c5f11213003ae</id>
<content type='text'>
Currently, the command parser tries to create a secondary batch exactly
as large as the original, and vmap both. This is open to abuse by
userspace using extremely large batch objects, but only executing very
short batches. For example, this would be if userspace were to implement
a command submission ringbuffer. However, we only need to allocate pages
for just the contents of the command sequence in the batch - all
relocations copied to the secondary batch will reference the original
batch and so there can be no access to the secondary batch outside of
the explicit execution region.

Testcase: igt/gem_exec_big #ivb,byt,hsw
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88308
Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Reviewed-by: John Harrison &lt;John.C.Harrison@Intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist</title>
<updated>2014-12-16T09:39:10Z</updated>
<author>
<name>Jordan Justen</name>
<email>jordan.l.justen@intel.com</email>
</author>
<published>2014-12-11T21:28:09Z</published>
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<id>urn:sha1:c61200c2c7e42fa6481638b7c8c3b5dc89c60eb9</id>
<content type='text'>
This will allow us to read the number of dispatched compute threads
for GL_ARB_pipeline_statistics_query.

Signed-off-by: Jordan Justen &lt;jordan.l.justen@intel.com&gt;
Cc: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Reviewed-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Tidy up execbuffer command parsing code</title>
<updated>2014-12-16T09:39:10Z</updated>
<author>
<name>Brad Volkin</name>
<email>bradley.d.volkin@intel.com</email>
</author>
<published>2014-12-11T20:13:12Z</published>
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<id>urn:sha1:7174537627836119e8b960afcc7139a138e02802</id>
<content type='text'>
Move it to a separate function since the main do_execbuffer function
already has so much going on.

v2:
- Move pin/unpin calls inside i915_parse_cmds() (Chris W, v4 7/7
  feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin &lt;bradley.d.volkin@intel.com&gt;
Reviewed-By: Jon Bloomfield &lt;jon.bloomfield@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Use batch length instead of object size in command parser</title>
<updated>2014-12-16T09:39:09Z</updated>
<author>
<name>Brad Volkin</name>
<email>bradley.d.volkin@intel.com</email>
</author>
<published>2014-12-11T20:13:10Z</published>
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<id>urn:sha1:b9ffd80ed659c559152c042e74741f4f60cac691</id>
<content type='text'>
Previously we couldn't trust the user-supplied batch length because
it came directly from userspace (i.e. untrusted code). It would have
affected what commands software parsed without regard to what hardware
would actually execute, leaving a potential hole.

With the parser now copying the user supplied batch buffer and writing
MI_NOP commands to any space after the copied region, we can safely use
the batch length input. This should be a performance win as the actual
batch length is frequently much smaller than the allocated object size.

v2: Fix handling of non-zero batch_start_offset

Issue: VIZ-4719
Signed-off-by: Brad Volkin &lt;bradley.d.volkin@intel.com&gt;
Reviewed-By: Jon Bloomfield &lt;jon.bloomfield@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Use batch pools with the command parser</title>
<updated>2014-12-16T09:39:09Z</updated>
<author>
<name>Brad Volkin</name>
<email>bradley.d.volkin@intel.com</email>
</author>
<published>2014-12-11T20:13:09Z</published>
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<id>urn:sha1:78a423772d08eb5a048765a883b5b5a308ea0d0f</id>
<content type='text'>
This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser and dispatches the copied
(shadow) batch to the hardware.

After this patch, the parser is in 'enabling' mode.

Note that performance takes a hit from the copy in some cases
and will likely need some work. At a rough pass, the memcpy
appears to be the bottleneck. Without having done a deeper
analysis, two ideas that come to mind are:
1) Copy sections of the batch at a time, as they are reached
   by parsing. Might improve cache locality.
2) Copy only up to the userspace-supplied batch length and
   memset the rest of the buffer. Reduces the number of reads.

v2:
- Remove setting the capacity of the pool
- One global pool instead of per-ring pools
- Replace batch_obj with shadow_batch_obj and hook into eb-&gt;vmas
- Memset any space in the shadow batch beyond what gets copied
- Rebased on execlist prep refactoring

v3:
- Rebase on chained batch handling
- Squash in setting the secure dispatch flag
- Add a note about the interaction w/secure dispatch pinning
- Check for request-&gt;batch_obj == NULL in i915_gem_free_request

v4:
- Fix read domains for shadow_batch_obj
- Remove the set_to_gtt_domain call from i915_parse_cmds
- ggtt_pin/unpin in the parser block to simplify error handling
- Check USES_FULL_PPGTT before setting DISPATCH_SECURE flag
- Remove i915_gem_batch_pool_put calls

v5:
- Move 'pending_read_domains |= I915_GEM_DOMAIN_COMMAND' after
  the parser (danvet, from v4 0/7 feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin &lt;bradley.d.volkin@intel.com&gt;
Reviewed-By: Jon Bloomfield &lt;jon.bloomfield@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Add MI_SET_APPID cmd to cmd parser tables</title>
<updated>2014-12-10T16:47:21Z</updated>
<author>
<name>Michael H. Nguyen</name>
<email>michael.h.nguyen@intel.com</email>
</author>
<published>2014-11-21T17:35:36Z</published>
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<id>urn:sha1:86ef630d53d6ae93f4a83fc3bfebaa111f8f83ce</id>
<content type='text'>
Was missing.

Issue: VIZ-4701
Signed-off-by: Michael H. Nguyen &lt;michael.h.nguyen@intel.com&gt;
Reviewed-by: Jon Bloomfield &lt;jon.bloomfield@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915: Flatten engine init control flow</title>
<updated>2014-12-03T08:35:29Z</updated>
<author>
<name>Daniel Vetter</name>
<email>daniel.vetter@ffwll.ch</email>
</author>
<published>2014-11-19T23:33:08Z</published>
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<id>urn:sha1:bfc882b4e30fbc169ecfe3508378623743806f56</id>
<content type='text'>
Now that sanity prevails and we have the clean split between software
init and starting the engines we can drop all the "have we allocate
this struct already?" nonsense.

Execlist code could benefit quite a bit more still, but that's for
another patch.

Reviewed-by: Dave Gordon &lt;david.s.gordon@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Add the predicate source registers to the register whitelist</title>
<updated>2014-11-14T09:29:24Z</updated>
<author>
<name>Neil Roberts</name>
<email>neil@linux.intel.com</email>
</author>
<published>2014-11-07T19:00:26Z</published>
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<id>urn:sha1:f1f55cc0556031c8ee3fe99dae7251e78b9b653b</id>
<content type='text'>
The predicate source registers are needed to implement conditional
rendering without stalling. The two source registers are used to load
the previous values of the PS_DEPTH_COUNT register saved from
PIPE_CONTROL commands. These can then be compared and used to set the
predicate enable bit via the MI_PREDICATE command.

The command parser version number is increased to 2 to make it easier
to detect the new functionality in user space.

Signed-off-by: Neil Roberts &lt;neil@linux.intel.com&gt;
Reviewed-by: Brad Volkin &lt;bradley.d.volkin@intel.com&gt; (v1)
Reviewed-by: Kenneth Graunke &lt;kenneth@whitecape.org&gt; (v1)
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'airlied/drm-next' into HEAD</title>
<updated>2014-11-10T09:55:35Z</updated>
<author>
<name>Daniel Vetter</name>
<email>daniel.vetter@ffwll.ch</email>
</author>
<published>2014-11-10T09:55:35Z</published>
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<id>urn:sha1:eb84f976c88d72cbcbe756df38d1f19be3db77d6</id>
<content type='text'>
Backmerge drm-next so that I can keep merging patches. Specifically I
want:
- atomic stuff, yay!
- eld parsing patch from Jani.

Signed-off-by: Daniel Vetter &lt;daniel.vetter@intel.com&gt;
</content>
</entry>
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