<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/i915/gvt/fb_decoder.c, branch linux-6.5.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.5.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.5.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2022-02-02T15:59:54Z</updated>
<entry>
<title>drm/i915: Only include i915_reg.h from .c files</title>
<updated>2022-02-02T15:59:54Z</updated>
<author>
<name>Matt Roper</name>
<email>matthew.d.roper@intel.com</email>
</author>
<published>2022-01-27T23:43:34Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=ce2fce2513c5c1076f2a2d6e977c0ac523aad5e3'/>
<id>urn:sha1:ce2fce2513c5c1076f2a2d6e977c0ac523aad5e3</id>
<content type='text'>
Several of our i915 header files, have been including i915_reg.h.  This
means that any change to i915_reg.h will trigger a full rebuild of
pretty much every file of the driver, even those that don't have any
kind of register access.  Let's delete the i915_reg.h include from all
headers and add an explicit include from the .c files that truly
need the register definitions; those that need a definition of
i915_reg_t for a function definition can get it from i915_reg_defs.h
instead.

We also remove two non-register #define's (VLV_DISPLAY_BASE and
GEN12_SFC_DONE_MAX) into i915_reg_defs.h to allow us to drop the
i915_reg.h include from a couple of headers.

There's probably a lot more header dependency optimization possible, but
the changes here roughly cut the number of files compiled after 'touch
i915_reg.h' in half --- a good first step.

Cc: Jani Nikula &lt;jani.nikula@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20220127234334.4016964-7-matthew.d.roper@intel.com
</content>
</entry>
<entry>
<title>drm/i915: Clean up pre-skl primary plane registers</title>
<updated>2022-01-24T09:38:26Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2022-01-21T11:30:31Z</published>
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<id>urn:sha1:428cb15d5b003102bc33d49f2ab31a6e4e785157</id>
<content type='text'>
Use REG_BIT() &amp; co. for the pre-skl primary plane registers.
Also give everything a consistent namespace.

v2: s/DSP/DISP/ to avoid confusion (José)
    Use DISP_WIDTH rather than DISP_POS_X for DSPSIZE (José)
    Deal with gvt

Cc: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20220121113036.23240-2-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Clean up cursor registers</title>
<updated>2022-01-18T02:03:27Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2021-12-01T15:25:49Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=348abd4cf353abb3aca8dc6ebb80ee84acc4f64e'/>
<id>urn:sha1:348abd4cf353abb3aca8dc6ebb80ee84acc4f64e</id>
<content type='text'>
Use REG_BIT() &amp; co. to polish the cursor plane registers.

v2: deal with gvt

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-12-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Clean up ivb+ sprite plane registers</title>
<updated>2022-01-18T01:51:16Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2021-12-01T15:25:46Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=2f609faf5bda9d828ce0229689227ba2edb1918b'/>
<id>urn:sha1:2f609faf5bda9d828ce0229689227ba2edb1918b</id>
<content type='text'>
Use REG_BIT() &amp; co. to polish the ivb+ sprite plane registers.

v2: deal with gvt

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-9-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Use REG_BIT() &amp; co. for universal plane bits</title>
<updated>2022-01-18T01:46:59Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2021-12-01T15:25:44Z</published>
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<id>urn:sha1:12d7d858e63d0769a91aab218828e0526c0ab49d</id>
<content type='text'>
Polish the skl+ universal plane register defines by
using REG_BIT() &amp; co.

The defines are also currently spread around in some
semi-random fashion. Collect them up into one place.

v2: deal with gvt

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-7-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Constify formats</title>
<updated>2022-01-12T07:52:37Z</updated>
<author>
<name>Rikard Falkeborn</name>
<email>rikard.falkeborn@gmail.com</email>
</author>
<published>2021-12-04T10:55:25Z</published>
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<id>urn:sha1:b17639c7f7fc1fbb23b761c38ba3233cd5d082d9</id>
<content type='text'>
These are never modified, so make them const to allow the compiler to
put them in read-only memory. WHile at it, make the description const
char* since it is never modified.

Signed-off-by: Rikard Falkeborn &lt;rikard.falkeborn@gmail.com&gt;
Signed-off-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20211204105527.15741-8-rikard.falkeborn@gmail.com
Reviewed-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Rename plane YUV order bits</title>
<updated>2021-12-03T10:49:02Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2021-12-01T15:25:40Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=62f887ae46861484c5ff2b8880c69403611c88b7'/>
<id>urn:sha1:62f887ae46861484c5ff2b8880c69403611c88b7</id>
<content type='text'>
Rename the YUV byte order bits to be a bit more consistent.

v2: Deal with gvt

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-3-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: replace IS_GEN and friends with GRAPHICS_VER</title>
<updated>2021-06-04T23:49:31Z</updated>
<author>
<name>Lucas De Marchi</name>
<email>lucas.demarchi@intel.com</email>
</author>
<published>2021-06-03T16:54:25Z</published>
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<id>urn:sha1:d8d123128c48721f8bcbd4700951f4cde723a0da</id>
<content type='text'>
This was done by the following semantic patch:

	@@ expression i915; @@
	- INTEL_GEN(i915)
	+ GRAPHICS_VER(i915)

	@@ expression i915; expression E; @@
	- INTEL_GEN(i915) &gt;= E
	+ GRAPHICS_VER(i915) &gt;= E

	@@ expression dev_priv; expression E; @@
	- !IS_GEN(dev_priv, E)
	+ GRAPHICS_VER(dev_priv) != E

	@@ expression dev_priv; expression E; @@
	- IS_GEN(dev_priv, E)
	+ GRAPHICS_VER(dev_priv) == E

	@@
	expression dev_priv;
	expression from, until;
	@@
	- IS_GEN_RANGE(dev_priv, from, until)
	+ IS_GRAPHICS_VER(dev_priv, from, until)

	@def@
	expression E;
	identifier id =~ "^gen$";
	@@
	- id = GRAPHICS_VER(E)
	+ ver = GRAPHICS_VER(E)

	@@
	identifier def.id;
	@@
	- id
	+ ver

It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".

Cc: intel-gvt-dev@lists.freedesktop.org
Cc: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20210603165428.3625495-5-lucas.demarchi@intel.com
</content>
</entry>
<entry>
<title>drm/i915/gvt: Wean gvt off using dev_priv</title>
<updated>2020-03-06T02:08:10Z</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2020-03-06T02:08:10Z</published>
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<id>urn:sha1:a61ac1e75105a077ec1efd6923ae3c619f862304</id>
<content type='text'>
Teach gvt to use intel_gt directly as it currently assumes direct HW
access.

[Zhenyu: rebase, fix compiling]

Cc: Ding Zhuocheng &lt;zhuocheng.ding@intel.com&gt;
Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Acked-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/20200304032307.2983-3-zhenyuw@linux.intel.com
</content>
</entry>
<entry>
<title>drm/i915/gvt: Don't use ggtt_validdate_range() with size=0</title>
<updated>2019-07-30T06:29:48Z</updated>
<author>
<name>Xiong Zhang</name>
<email>xiong.y.zhang@intel.com</email>
</author>
<published>2019-05-27T05:45:52Z</published>
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<id>urn:sha1:c25144098bee19b089c8a37c54517bf467f06403</id>
<content type='text'>
Use vgpu_gmadr_is_valid() directly instead.

Reviewed-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Xiong Zhang &lt;xiong.y.zhang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
</feed>
