<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/i915/gvt/display.c, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-03-30T06:47:19Z</updated>
<entry>
<title>drm/i915/gvt: Disable primary/sprite/cursor plane at virtual display initialization</title>
<updated>2018-03-30T06:47:19Z</updated>
<author>
<name>Xiong Zhang</name>
<email>xiong.y.zhang@intel.com</email>
</author>
<published>2018-03-27T21:30:14Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=65eff272330c72689fb5e20dd6491826fd87a39c'/>
<id>urn:sha1:65eff272330c72689fb5e20dd6491826fd87a39c</id>
<content type='text'>
Much error exist in host dmesg during guest boot up with loca display
enabled.
gvt: vgpu 1: invalid range gmadr 0x0 size 0x0

This error happens when qemu get dmabuf info in case that the virtual
display plane is enabled but its base address is an invalid 0, such
case may be true before guest enable its plane. At this moment, its
state is copied from host where the plane may be enabled.

This patch disable primary/sprite/cursor plane at virtual display
initialization, so intel_vgpu_decode_primary/cursor/sprite could
return early as plane is disabled, then plane base check is skipped and
error message disapper.

Signed-off-by: Xiong Zhang &lt;xiong.y.zhang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: cleanup usage for typed mmio reg vs. offset</title>
<updated>2017-12-22T08:33:03Z</updated>
<author>
<name>Zhenyu Wang</name>
<email>zhenyuw@linux.intel.com</email>
</author>
<published>2017-12-19T05:02:51Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=90551a1296d4dbe0dccc4c3cb5e57e7f2c929009'/>
<id>urn:sha1:90551a1296d4dbe0dccc4c3cb5e57e7f2c929009</id>
<content type='text'>
We had previous hack that tried to accept either i915_reg_t or offset
value to access vGPU virtual/shadow regs which broke that purpose to
be type safe in context. This one trys to explicitly separate the usage
of typed mmio reg with real offset.

Old vgpu_vreg(offset) helper is used only for offset now with new
vgpu_vreg_t(reg) is used for i915_reg_t only. Convert left usage
of that to new helper.

Also fixed left KASAN warning issues caused by previous hack.

v2: rebase, fixup against recent mmio switch change

Reviewed-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Fix pipe A enable as default for vgpu</title>
<updated>2017-12-22T08:33:00Z</updated>
<author>
<name>Xiaolin Zhang</name>
<email>xiaolin.zhang@intel.com</email>
</author>
<published>2017-12-05T06:45:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=4e889d62b89d00e641d588eafed7e721e0a46090'/>
<id>urn:sha1:4e889d62b89d00e641d588eafed7e721e0a46090</id>
<content type='text'>
observed igt drv_module_reload test case failure on 4.15.0
rc2 kernel with panic due to no active pipe available.

the gpu will reset during unload/load and make pipe config reg
lost which can cause kernel panic issue happen.

this patch is to move pipe enabling to emulate_mointor_status_chagne
to handle vgpu reset case as well.

Fixes: 7e6059020894 ("drm/i915/gvt: enabled pipe A default on creating vgpu")
Signed-off-by: Xiaolin Zhang &lt;xiaolin.zhang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
(cherry picked from commit f5f00e7dcc4161f07b76ff1a854e8b1ea7a1ed41)
</content>
</entry>
<entry>
<title>Merge airlied/drm-next into drm-intel-next-queued</title>
<updated>2017-12-08T18:15:30Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2017-12-08T18:15:30Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=6647852abc1fd74e9c5e0dcf404ea4cb9c929630'/>
<id>urn:sha1:6647852abc1fd74e9c5e0dcf404ea4cb9c929630</id>
<content type='text'>
Chris requested this backmerge for a reconciliation on
drm_print.h between drm-misc-next and drm-intel-next-queued

Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Add framebuffer decoder support</title>
<updated>2017-12-04T03:24:33Z</updated>
<author>
<name>Tina Zhang</name>
<email>tina.zhang@intel.com</email>
</author>
<published>2017-11-23T08:26:32Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9f31d1063b434c2d54317461d78285b08538c01a'/>
<id>urn:sha1:9f31d1063b434c2d54317461d78285b08538c01a</id>
<content type='text'>
This patch is to introduce the framebuffer decoder which can decode guest
OS's framebuffer information, including primary, cursor and sprite plane.

v16:
- rebase to 4.14.0-rc6.

v14:
- refine pixel format table. (Zhenyu)

v9:
- move drm format change to a separate patch. (Xiaoguang)

v8:
- fix a bug in decoding primary plane. (Tina)

v7:
- refine framebuffer decoder code. (Zhenyu)

Signed-off-by: Tina Zhang &lt;tina.zhang@intel.com&gt;
Cc: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: enabled pipe A default on creating vgpu</title>
<updated>2017-11-28T09:24:30Z</updated>
<author>
<name>Xiaolin Zhang</name>
<email>xiaolin.zhang@intel.com</email>
</author>
<published>2017-11-16T08:54:23Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7e60590208942de856fd43956ccebd19e71d686f'/>
<id>urn:sha1:7e60590208942de856fd43956ccebd19e71d686f</id>
<content type='text'>
when i915 driver unloading, it will shutdown all CRTCs and
it will introudce kernel panic when conducting igt drv_module_reload
test case under guest environment (bug reported by XENGT-468) as below:

BUG: unable to handle kernel NULL pointer dereference at 0000000000000070
IP: intel_edp_backlight_off+0xe/0x7c [i915]
RIP: 0010:intel_edp_backlight_off+0xe/0x7c [i915]
Call Trace:
 intel_disable_ddi+0xb3/0xbc [i915]
 intel_modeset_setup_hw_state+0x654/0xb4c [i915]
 intel_modeset_init+0x9f1/0xe69 [i915]
 ? intel_i2c_reset+0x3d/0x40 [i915]
 ? intel_setup_gmbus+0xba/0x249 [i915]
 i915_driver_load+0xae5/0xcc0 [i915]
 i915_pci_probe+0x3a/0x3c [i915]
 local_pci_probe+0x38/0x7b
 pci_device_probe+0xec/0x12b
 driver_probe_device+0x134/0x294
 __driver_attach+0x6a/0x8c
 ? driver_probe_device+0x294/0x294
 bus_for_each_dev+0x68/0x80
 driver_attach+0x19/0x1b
 bus_add_driver+0xea/0x1d3
 ? 0xffffffffa03cd000
 driver_register+0x85/0xc1
 ? 0xffffffffa03cd000
 __pci_register_driver+0x55/0x57
 i915_init+0x57/0x5a [i915]
 do_one_initcall+0x8a/0x12e
 ? __vunmap+0x8d/0x93
 ? kmem_cache_alloc_trace+0x96/0x11c
 do_init_module+0x5a/0x1e1

in this case, active connector detected but no active pipe
available, so it will hang to disable connector.

to fix, on vgpu creating, to report active pipe available for
guest.

Signed-off-by: Xiaolin Zhang &lt;xiaolin.zhang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-intel-next-2017-08-18' of git://anongit.freedesktop.org/git/drm-intel into drm-next</title>
<updated>2017-08-22T00:03:07Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2017-08-22T00:03:07Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=735f463af70e9601881ec879961ec42aef051733'/>
<id>urn:sha1:735f463af70e9601881ec879961ec42aef051733</id>
<content type='text'>
Final pile of features for 4.14

- New ioctl to change NOA configurations, plus prep (Lionel)
- CCS (color compression) scanout support, based on the fancy new
  modifier additions (Ville&amp;Ben)
- Document i915 register macro style (Jani)
- Many more gen10/cnl patches (Rodrigo, Pualo, ...)
- More gpu reset vs. modeset duct-tape to restore the old way.
- prep work for cnl: hpd_pin reorg (Rodrigo), support for more power
  wells (Imre), i2c pin reorg (Anusha)
- drm_syncobj support (Jason Ekstrand)
- forcewake vs gpu reset fix (Chris)
- execbuf speedup for the no-relocs fastpath, anv/vk low-overhead ftw (Chris)
- switch to idr/radixtree instead of the resizing ht for execbuf id-&gt;vma
  lookups (Chris)

gvt:
- MMIO save/restore optimization (Changbin)
- Split workload scan vs. dispatch for more parallel exec (Ping)
- vGPU full 48bit ppgtt support (Joonas, Tina)
- vGPU hw id expose for perf (Zhenyu)

Bunch of work all over to make the igt CI runs more complete/stable.
Watch https://intel-gfx-ci.01.org/tree/drm-tip/shards-all.html for
progress in getting this ready. Next week we're going into production
mode (i.e. will send results to intel-gfx) on hsw, more platforms to
come.

Also, a new maintainer tram, I'm stepping out. Huge thanks to Jani for
being an awesome co-maintainer the past few years, and all the best
for Jani, Joonas&amp;Rodrigo as the new maintainers!

* tag 'drm-intel-next-2017-08-18' of git://anongit.freedesktop.org/git/drm-intel: (179 commits)
  drm/i915: Update DRIVER_DATE to 20170818
  drm/i915/bxt: use NULL for GPIO connection ID
  drm/i915: Mark the GT as busy before idling the previous request
  drm/i915: Trivial grammar fix s/opt of/opt out of/ in comment
  drm/i915: Replace execbuf vma ht with an idr
  drm/i915: Simplify eb_lookup_vmas()
  drm/i915: Convert execbuf to use struct-of-array packing for critical fields
  drm/i915: Check context status before looking up our obj/vma
  drm/i915: Don't use MI_STORE_DWORD_IMM on Sandybridge/vcs
  drm/i915: Stop touching forcewake following a gen6+ engine reset
  MAINTAINERS: drm/i915 has a new maintainer team
  drm/i915: Split pin mapping into per platform functions
  drm/i915/opregion: let user specify override VBT via firmware load
  drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.
  drm/i915/gen10: implement gen 10 watermarks calculations
  drm/i915/cnl: Fix LSPCON support.
  drm/i915/vbt: ignore extraneous child devices for a port
  drm/i915/cnl: Setup PAT Index.
  drm/i915/edp: Allow alternate fixed mode for eDP if available.
  drm/i915: Add support for drm syncobjs
  ...
</content>
</entry>
<entry>
<title>drm/i915/hsw+: Add has_fuses power well attribute</title>
<updated>2017-07-27T07:38:53Z</updated>
<author>
<name>Imre Deak</name>
<email>imre.deak@intel.com</email>
</author>
<published>2017-07-11T20:42:35Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b2891eb2531e5e0d251febd0a395d758111790d4'/>
<id>urn:sha1:b2891eb2531e5e0d251febd0a395d758111790d4</id>
<content type='text'>
The pattern of a power well backing a set of fuses whose initialization
we need to wait for during power well enabling is common to all GEN9+
platforms. Adding support for this to the HSW power well enable helper
allows us to use the HSW/BDW power well code for GEN9+ as well in a
follow-up patch.

v2:
- Use an enum for power gates instead of raw numbers. (Ville)

Signed-off-by: Imre Deak &lt;imre.deak@intel.com&gt;
Reviewed-by: Arkadiusz Hiler &lt;arkadiusz.hiler@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-6-imre.deak@intel.com
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Fix the vblank timer close issue after shutdown VMs in reverse</title>
<updated>2017-07-17T09:09:04Z</updated>
<author>
<name>fred gao</name>
<email>fred.gao@intel.com</email>
</author>
<published>2017-07-17T06:52:05Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=f43aa31fe7dc43b808ec619b0d407180cd3725c0'/>
<id>urn:sha1:f43aa31fe7dc43b808ec619b0d407180cd3725c0</id>
<content type='text'>
Once the Windows guest is shutdown, the display pipe will be disabled
and intel_gvt_check_vblank_emulation will be called to check if the
vblank timer is turned off. Given the scenario of creating VM1 ,VM2,
destoying VM2 in current code, VM1 has pipe enabled and continues to
check VM2, the flag have_enabled_pipe is always false since all the VM2
pipes are disabled, so the vblank timer will be canceled and TDR happens
in Windows VM1 guest due to the vsync timeout.

In this patch the vblank timer will be never canceled once one pipe is
enabled.

v2:
- remove have_enabled_pipe flag and check pipe enabled directly. (Zhenyu)

Cc: Wang Hongbo &lt;hongbo.wang@intel.com&gt;
Signed-off-by: fred gao &lt;fred.gao@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Don't read ADPA_CRT_HOTPLUG_MONITOR from host</title>
<updated>2017-06-27T09:29:25Z</updated>
<author>
<name>Xiong Zhang</name>
<email>xiong.y.zhang@intel.com</email>
</author>
<published>2017-06-27T18:03:16Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=75e64ff2c2f5ce1ae5b47b2f372fe5b9dc99f5a9'/>
<id>urn:sha1:75e64ff2c2f5ce1ae5b47b2f372fe5b9dc99f5a9</id>
<content type='text'>
When host connects a crt screen, linux guest will detect two
screens: crt and dp. This is wrong as linux guest has only
one dp.

In order to avoid guest get host crt screen, we should set
ADPA_CRT_HOTPLUG_MONITOR to none. But MMIO_RO(PCH_ADPA) prevent
from that. So MMIO_DH should be used instead of MMIO_RO.

v2: Clear its staus to none at initialize, so guest don't
    get host crt.(Zhangyu)
v3: SKL doesn't have this register, limit it to pre_skl.(xiong)

Signed-off-by: Xiong Zhang &lt;xiong.y.zhang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
</feed>
