<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/i915/gvt/debug.h, branch linux-6.5.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.5.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.5.y'/>
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<updated>2017-11-16T03:48:34Z</updated>
<entry>
<title>drm/i915/gvt: Make gvt_vgpu_err use pr_err</title>
<updated>2017-11-16T03:48:34Z</updated>
<author>
<name>Changbin Du</name>
<email>changbin.du@intel.com</email>
</author>
<published>2017-11-02T05:33:32Z</published>
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<id>urn:sha1:c982c45db6a78e1c23a416785fe920542ae1f33e</id>
<content type='text'>
gvt_vgpu_err means something goes wrong. We need the error propagates to
kernel message by default.

Signed-off-by: Changbin Du &lt;changbin.du@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: Use dyndbg for gvt debug info</title>
<updated>2017-11-16T03:46:52Z</updated>
<author>
<name>Shuo Liu</name>
<email>shuo.a.liu@intel.com</email>
</author>
<published>2017-09-21T00:02:31Z</published>
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<id>urn:sha1:a34e8def4d9152123582a37a3660c2092e37ceed</id>
<content type='text'>
It's better enable/disable and classify gvt debug info dynamically.
This patch change it to dyndbg so can be dynamically enable/disable
each item. All gvt log can be enabled by,
 $ echo 'file *gvt* +p' &gt; /sys/kernel/debug/dynamic_debug/control

Signed-off-by: Shuo Liu &lt;shuo.a.liu@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: replace the gvt_err with gvt_vgpu_err</title>
<updated>2017-03-17T08:46:45Z</updated>
<author>
<name>Tina Zhang</name>
<email>tina.zhang@intel.com</email>
</author>
<published>2017-03-10T09:26:53Z</published>
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<id>urn:sha1:695fbc08d80f93ecca18a1abd8f52c2ab77fdc8d</id>
<content type='text'>
gvt_err should be used only for the very few critical error message
during host i915 drvier initialization. This patch
1. removes the redundant gvt_err;
2. creates a new gvt_vgpu_err to show errors caused by vgpu;
3. replaces the most gvt_err with gvt_vgpu_err;
4. leaves very few gvt_err for dumping gvt error during host gvt
   initialization.

v2. change name to gvt_vgpu_err and add vgpu id to the message. (Kevin)
    add gpu id to gvt_vgpu_err. (Zhi)
v3. remove gpu id from gvt_vgpu_err caller. (Zhi)
v4. add vgpu check to the gvt_vgpu_err macro. (Zhiyuan)
v5. add comments for v3 and v4.
v6. split the big patch into two, with this patch only for checking
    gvt_vgpu_err. (Zhenyu)
v7. rebase to staging branch
v8. rebase to fix branch

Signed-off-by: Tina Zhang &lt;tina.zhang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: vGPU command scanner</title>
<updated>2016-10-14T10:15:25Z</updated>
<author>
<name>Zhi Wang</name>
<email>zhi.a.wang@intel.com</email>
</author>
<published>2016-05-03T22:26:57Z</published>
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<id>urn:sha1:be1da7070aeaee23ff659c1a8cd992789ff86da4</id>
<content type='text'>
This patch introduces a command scanner to scan guest command buffers.

Signed-off-by: Yulei Zhang &lt;yulei.zhang@intel.com&gt;
Signed-off-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: vGPU context switch</title>
<updated>2016-10-14T10:15:13Z</updated>
<author>
<name>Zhi Wang</name>
<email>zhi.a.wang@intel.com</email>
</author>
<published>2016-05-01T23:02:37Z</published>
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<id>urn:sha1:178657139307126b22d226df0823223d6dfe91ba</id>
<content type='text'>
As different VM may configure different render MMIOs when executing
workload, to schedule workloads between different VM, the render MMIOs
have to be switched.

Signed-off-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: vGPU workload scheduler</title>
<updated>2016-10-14T10:14:50Z</updated>
<author>
<name>Zhi Wang</name>
<email>zhi.a.wang@intel.com</email>
</author>
<published>2016-05-01T11:42:16Z</published>
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<id>urn:sha1:e473405783c064a9d859d108010581bae8e9af40</id>
<content type='text'>
This patch introduces the vGPU workload scheduler routines.

GVT workload scheduler is responsible for picking and executing GVT workload
from current scheduled vGPU. Before the workload is submitted to host i915,
the guest execlist context will be shadowed in the host GVT shadow context.
the instructions in guest ring buffer will be copied into GVT shadow ring
buffer. Then GVT-g workload scheduler will scan the instructions in guest
ring buffer and submit it to host i915.

Signed-off-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: vGPU execlist virtualization</title>
<updated>2016-10-14T10:14:28Z</updated>
<author>
<name>Zhi Wang</name>
<email>zhi.a.wang@intel.com</email>
</author>
<published>2016-05-01T06:48:25Z</published>
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<id>urn:sha1:8453d674ae7e63f629a91fe4124df7a7dc9c74cd</id>
<content type='text'>
This patch introduces the vGPU execlist virtualization.

Under virtulization environment, HW execlist interface are fully emulated
including virtual CSB emulation, virtual execlist emulation. The framework
will emulate the virtual CSB according to the guest workload running status

Signed-off-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: vGPU display virtualization</title>
<updated>2016-10-14T10:13:06Z</updated>
<author>
<name>Zhi Wang</name>
<email>zhi.a.wang@intel.com</email>
</author>
<published>2016-04-25T22:28:56Z</published>
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<id>urn:sha1:04d348ae3f0aea6523bc3b0688b5fc90c1c60d0e</id>
<content type='text'>
This patch introduces the GVT-g display virtualization.

It consists a collection of display MMIO handlers, like power well register
handler, pipe register handler, plane register handler, which will emulate
all display MMIOs behavior to support virtual mode setting sequence for
guest.

Signed-off-by: Bing Niu &lt;bing.niu@intel.com&gt;
Signed-off-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: vGPU MMIO virtualization</title>
<updated>2016-10-14T10:12:59Z</updated>
<author>
<name>Zhi Wang</name>
<email>zhi.a.wang@intel.com</email>
</author>
<published>2016-09-02T05:33:29Z</published>
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<id>urn:sha1:e39c5add322184de3be052d438dfd24375bfeaea</id>
<content type='text'>
This patch introduces the generic vGPU MMIO emulation intercept
framework.  The MPT modules will request GVT-g core logic to
emulate MMIO read/write through IO emulation operations
callback when hypervisor trapped a guest GTTMMIO read/write.

Signed-off-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/gvt: vGPU graphics memory virtualization</title>
<updated>2016-10-14T10:12:33Z</updated>
<author>
<name>Zhi Wang</name>
<email>zhi.a.wang@intel.com</email>
</author>
<published>2016-03-28T15:23:16Z</published>
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<id>urn:sha1:2707e44466881d6b0a8ed05a429dcf0940c22f60</id>
<content type='text'>
The vGPU graphics memory emulation framework is responsible for graphics
memory table virtualization. Under virtualization environment, a VM will
populate the page table entry with guest page frame number(GPFN/GFN), while
HW needs a page table filled with MFN(Machine frame number). The
relationship between GFN and MFN(Machine frame number) is managed by
hypervisor, while GEN HW doesn't have such knowledge to translate a GFN.

To solve this gap, shadow GGTT/PPGTT page table is introdcued.

For GGTT, the GFN inside the guest GGTT page table entry will be translated
into MFN and written into physical GTT MMIO registers when guest write
virtual GTT MMIO registers.

For PPGTT, a shadow PPGTT page table will be created and write-protected
translated from guest PPGTT page table.  And the shadow page table root
pointers will be written into the shadow context after a guest workload
is shadowed.

vGPU graphics memory emulation framework consists:

- Per-GEN HW platform page table entry bits extract/de-extract routines.
- GTT MMIO register emulation handlers, which will call hypercall to do
GFN-&gt;MFN translation when guest write GTT MMIO register
- PPGTT shadow page table routines, e.g. shadow create/destroy/out-of-sync

Signed-off-by: Zhi Wang &lt;zhi.a.wang@intel.com&gt;
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
</content>
</entry>
</feed>
