kernel/drivers/gpu/drm/bridge/samsung-dsim.c, branch linux-rolling-lts

drm/bridge: samsung-dsim: Fix memory leak in error path

2026-03-19T15:08:33Z

commit 803ec1faf7c1823e6e3b1f2aaa81be18528c9436 upstream. In samsung_dsim_host_attach(), drm_bridge_add() is called to add the bridge. However, if samsung_dsim_register_te_irq() or pdata->host_ops->attach() fails afterwards, the function returns without removing the bridge, causing a memory leak. Fix this by adding proper error handling with goto labels to ensure drm_bridge_remove() is called in all error paths. Also ensure that samsung_dsim_unregister_te_irq() is called if the attach operation fails after the TE IRQ has been registered. samsung_dsim_unregister_te_irq() function is moved without changes to be before samsung_dsim_host_attach() to avoid forward declaration. Fixes: e7447128ca4a ("drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge") Cc: stable@vger.kernel.org Signed-off-by: Osama Abdelkader Reviewed-by: Luca Ceresoli Link: https://patch.msgid.link/20260209184115.10937-1-osama.abdelkader@gmail.com Signed-off-by: Luca Ceresoli Signed-off-by: Greg Kroah-Hartman

drm/bridge: samsung-dsim: add driver support for exynos7870 DSIM bridge

2025-09-15T10:55:15Z

Add support for Exynos7870's DSIM IP block in the bridge driver. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae

drm/bridge: samsung-dsim: add ability to define clock names for every variant

2025-09-15T10:55:10Z

Presently, all devices refer to clock names from a single array. The only controlling parameter is the number of clocks (num_clks field of samsung_dsim_driver_data) which uses the first n clocks of that array. As new devices are added, this approach turns out to be cumbersome. Separate the clock names in individual arrays required by each variant, in a struct clk_bulk_data. Add a pointer field to the driver data struct which points to their respective clock names, and rework the clock usage code to use the clk_bulk_* API instead. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae

drm/bridge: samsung-dsim: increase timeout value for PLL_STABLE

2025-09-15T10:55:07Z

Exynos7870's DSIM requires more time to stabilize its PLL. The current timeout value, 1000, doesn't suffice. Increase the value to 3000, which is just about enough as observed experimentally. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae

drm/bridge: samsung-dsim: allow configuring the PLL_STABLE bit

2025-09-15T10:55:04Z

The PLL_STABLE bit of DSIM_DPHY_STATUS is hardcoded to BIT(31), but Exynos7870's DSIM has it in BIT(24) as per downstream kernel sources. In order to support both, move this bit value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae

drm/bridge: samsung-dsim: allow configuring PLL_M and PLL_S offsets

2025-09-15T10:55:01Z

Currently, PLL_P offset of DSIM_PLLCTRL is configurable in the driver data, while PLL_M and PLL_S offsets are hardcoded as 4-bit and 1-bit offsets respectively, but Exynos7870's DSIM have them at 3-bit and 0-bit offsets as per downstream kernel sources. In order to support both, move both offset values to the driver data struct and define it for every driver compatible. Reference the values from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae

drm/bridge: samsung-dsim: allow configuring the VIDEO_MODE bit

2025-09-15T10:54:59Z

The VIDEO_MODE bit of DSIM_CONFIG is hardcoded to BIT(25), but Exynos7870's DSIM has it in BIT(18) as per downstream kernel sources. In order to support both, move this bit value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae

drm/bridge: samsung-dsim: allow configuring the MAIN_VSA offset

2025-09-15T10:54:52Z

The MAIN_VSA offset of DSIM_MSYNC is hardcoded to a 22-bit offset, but Exynos7870's DSIM has it in a 16-bit offset as per the downstream kernel sources. In order to support both, move this offset value to the driver data struct and define it for every driver compatible. Reference the value from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae

drm/bridge: samsung-dsim: allow configuring bits and offsets of CLKCTRL register

2025-09-15T10:54:49Z

DSIM_CLKCTRL bit and offset values hardcoded in the driver: name | bit/offset value --------------------------+----------------- DSIM_LANE_ESC_CLK_EN_CLK | 19 DSIM_LANE_ESC_CLK_EN_DATA | 20 DSIM_BYTE_CLKEN | 24 DSIM_ESC_CLKEN | 28 DSIM_TX_REQUEST_HSCLK | 31 DSIM_CLKCTRL bit and offset values in Exynos7870 DSIM as per downstream kernel sources: name | bit/offset value --------------------------+----------------- DSIM_LANE_ESC_CLK_EN_CLK | 8 DSIM_LANE_ESC_CLK_EN_DATA | 9 DSIM_BYTE_CLKEN | 17 DSIM_ESC_CLKEN | 16 DSIM_TX_REQUEST_HSCLK | 20 In order to support both, move all values to the driver data struct and define it for every driver compatible. Reference the values from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae

drm/bridge: samsung-dsim: add flag to control header FIFO wait

2025-09-15T10:54:47Z

Exynos7870's DSIM device doesn't require waiting for the header FIFO during a MIPI DSI transfer. Add a flag in the driver data in order to control said behavior. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Inki Dae