<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/arm/malidp_hw.h, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
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<updated>2018-03-14T11:41:01Z</updated>
<entry>
<title>drm: mali-dp: Add YUV-&gt;RGB conversion support for video layers</title>
<updated>2018-03-14T11:41:01Z</updated>
<author>
<name>Mihail Atanassov</name>
<email>mihail.atanassov@arm.com</email>
</author>
<published>2017-11-07T15:30:46Z</published>
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<id>urn:sha1:6e810eb508f4b937bc2a718bd4e5cd74cca55500</id>
<content type='text'>
Internally Mali DP uses an RGB pipeline so video layers that support
YUV input buffers need to convert the input data to RGB. The YUV
buffers can have various encodings and this patch introduces support
for BT.601, BT.709 and BT.2020 encodings, both limited and full ranges.

This patch adds support for specifying the color encoding of the
input buffers for the planes that are backed by the video layers
and programs the YUV2RGB coefficients into hardware based on the
selected encoding.

Signed-off-by: Mihail Atanassov &lt;mihail.atanassov@arm.com&gt;
[updated to use standard properties]
Signed-off-by: Liviu Dudau &lt;liviu.dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm/mali-dp: Rotated planes need a larger pitch size.</title>
<updated>2018-03-14T11:38:02Z</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@arm.com</email>
</author>
<published>2017-12-05T16:51:03Z</published>
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<id>urn:sha1:fcad73b9b1fb9580fd43f1349fd8ab34d5d456e9</id>
<content type='text'>
Rotated planes need a pitch size that is aligned to 8 bytes
for older DP500 and DP550 and at least 64 bytes for DP650. Replace
the malidp_hw_pitch_valid() function with one that calculates
the correct pitch alignment to take into account rotation.

Signed-off-by: Liviu Dudau &lt;liviu.dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm: mali-dp: Separate static internal data into a read-only structure.</title>
<updated>2017-11-24T15:42:59Z</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@arm.com</email>
</author>
<published>2017-08-31T14:48:43Z</published>
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<id>urn:sha1:a6993b215a719ad5758c1bced5f8df95add070bf</id>
<content type='text'>
The malidp_hw_device structure that the driver uses to handle the
differences between versions of the IP contains both non-changeable
data and fields that get updated at probe time. Previously we were
copying the read-only part into allocated memory, but that can be
completely avoided by splitting the structure into a read-only part
and keeping the runtime modifiable fields into the old structure.

Reviewed-by: Brian Starkey &lt;brian.starkey@arm.com&gt;
Reviewed-by: Gustavo Padovan &lt;gustavo.padovan@collabora.com&gt;
Signed-off-by: Liviu Dudau &lt;liviu.dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm: mali-dp: Check the mclk rate and allow up/down scaling</title>
<updated>2017-04-24T12:28:09Z</updated>
<author>
<name>Mihail Atanassov</name>
<email>mihail.atanassov@arm.com</email>
</author>
<published>2017-02-13T15:09:01Z</published>
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<id>urn:sha1:c2e7f82d336a451ebb904b8bf9a5a558cf16c39b</id>
<content type='text'>
When downscaling, mclk needs to be sufficiently higher than pxlclk in
order to be able to fetch the higher-resolution data and produce output
pixels. When not scaling, or when upscaling, mclk can be equal to
pxlclk. Since the driver doesn't control mclk, just ensure that the
requirement is satisfied with the current clock rate.

Signed-off-by: Mihail Atanassov &lt;mihail.atanassov@arm.com&gt;
Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm: mali-dp: Enable image enhancement when scaling</title>
<updated>2017-04-24T12:28:08Z</updated>
<author>
<name>Mihail Atanassov</name>
<email>mihail.atanassov@arm.com</email>
</author>
<published>2017-02-06T12:20:56Z</published>
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<id>urn:sha1:0274e6a0ba9a4994a449fcd3483ef530027e152f</id>
<content type='text'>
Apply image enhacement when we are upscaling by a factor of 2
or more in either direction.

Signed-off-by: Mihail Atanassov &lt;mihail.atanassov@arm.com&gt;
Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm: mali-dp: Add plane upscaling support</title>
<updated>2017-04-24T12:28:08Z</updated>
<author>
<name>Mihail Atanassov</name>
<email>mihail.atanassov@arm.com</email>
</author>
<published>2017-02-13T15:14:05Z</published>
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<id>urn:sha1:28ce675b74742cae1c815970347267b45dc73a8a</id>
<content type='text'>
Enable the scaling engine for upscaling a single plane using the polyphase
scaler. No image enhancement support or downscaling yet*, and composition
result scaling is not implemented.

* Downscaling a plane requires mclk &gt; pxlclk.

Signed-off-by: Mihail Atanassov &lt;mihail.atanassov@arm.com&gt;
Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm: mali-dp: Add CTM support</title>
<updated>2017-04-24T09:45:34Z</updated>
<author>
<name>Mihail Atanassov</name>
<email>mihail.atanassov@arm.com</email>
</author>
<published>2017-02-13T12:49:03Z</published>
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<id>urn:sha1:6954f24588ebddc2e3c840103f02d1fe7e65a2d6</id>
<content type='text'>
All DPs have a COLORADJ matrix which is applied prior to output gamma.
Attach that to the CTM property. Also, ensure the input CTM's coefficients
can fit in the DP registers' Q3.12 format.

Signed-off-by: Mihail Atanassov &lt;mihail.atanassov@arm.com&gt;
Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm: mali-dp: enable gamma support</title>
<updated>2017-04-24T09:45:34Z</updated>
<author>
<name>Mihail Atanassov</name>
<email>mihail.atanassov@arm.com</email>
</author>
<published>2017-02-01T14:48:50Z</published>
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<id>urn:sha1:02725d31371b66b97bc58b2a81f0c6dc40970598</id>
<content type='text'>
Add gamma via the DRM GAMMA_LUT/GAMMA_LUT_SIZE CRTC
properties. The expected LUT size is 4096 in order
to produce as accurate a set of segments as possible.

This version uses only the green channel's gamma curve
to set the hardware curve on DP550/650. For the sake of
simplicity, it uses the same table of coefficients for
all 3 curves on DP500.

Signed-off-by: Mihail Atanassov &lt;mihail.atanassov@arm.com&gt;
Signed-off-by: Liviu Dudau &lt;liviu.dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm: mali-dp: Enable power management for the device.</title>
<updated>2017-04-24T09:45:33Z</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@arm.com</email>
</author>
<published>2017-03-22T10:44:57Z</published>
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<id>urn:sha1:85f6421889eca68ceb0a0403c4c00b2eaf3c16e0</id>
<content type='text'>
Enable runtime and system Power Management. Clocks are now managed
from malidp_crtc_{enable,disable} functions. Suspend-to-RAM tested
as working on Juno.

Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
</content>
</entry>
<entry>
<title>drm: mali-dp: fix stride setting for multi-plane formats</title>
<updated>2017-01-26T15:46:19Z</updated>
<author>
<name>Mihail Atanassov</name>
<email>mihail.atanassov@arm.com</email>
</author>
<published>2017-01-23T15:24:35Z</published>
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<id>urn:sha1:83d642ee6dbec57ef1639a3de1e383fbfc5c44ec</id>
<content type='text'>
Hardware has multiple (2 or 3, depending on model) stride
registers per layer; add a function that correctly takes that
into account. On hardware that only has 2 stride registers,
ensure that 3-plane (YUV) content has identical strides
for both chroma planes.

Signed-off-by: Mihail Atanassov &lt;mihail.atanassov@arm.com&gt;
[Removed smart layer stride setup, comment and commit message clarifications]
Signed-off-by: Liviu Dudau &lt;Liviu.Dudau@arm.com&gt;
</content>
</entry>
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