kernel/drivers/gpu/drm/amd/include, branch linux-6.12.y

drm/amdgpu: Add additional DCE6 SCL registers

2025-10-19T14:33:42Z

[ Upstream commit 507296328b36ffd00ec1f4fde5b8acafb7222ec7 ] Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)") Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu: Enable MES lr_compute_wa by default

2025-10-12T10:57:17Z

commit 1fb710793ce2619223adffaf981b1ff13cd48f17 upstream. The MES set resources packet has an optional bit 'lr_compute_wa' which can be used for preventing MES hangs on long compute jobs. Set this bit by default. Co-developed-by: Yifan Zhang Signed-off-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/include : Update MES v12 API for fence update

2025-10-12T10:57:17Z

commit 15d8c92f107c17c2e585cb4888c67873538f9722 upstream. MES fence_value will be updated in fence_addr if API success, otherwise upper 32 bit will be used to indicate error code. In any case, MES will trigger an EOP interrupt with 0xb1 as context id in the interrupt cookie Signed-off-by: Shaoyun Liu Acked-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/include : MES v11 and v12 API header update

2025-10-12T10:57:17Z

commit 1c687c0da9efb7c627793483a8927554764e7a55 upstream. MES requires driver set cleaner_shader_fence_mc_addr for cleaner shader support. Signed-off-by: Shaoyun Liu Acked-by: Alex Deucher Acked-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd : Update MES API header file for v11 & v12

2025-10-12T10:57:17Z

commit ce4971388c79d36b3f50f607c3278dbfae6c789b upstream. New features require the new fields defines Signed-off-by: Shaoyun Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amdgpu: Set snoop bit for SDMA for MI series

2025-05-29T09:02:52Z

[ Upstream commit 3394b1f76d3f8adf695ceed350a5dae49003eb37 ] SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for this to happen. v2: Missed a few mmhub_v9_4. Added now. v3: Calculate hub offset once since it doesn't change inside the loop Modified function names based on review comments. Signed-off-by: Harish Kasiviswanathan Reviewed-by: Philip Yang Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd: Add some missing straps from NBIO 7.11.0

2024-12-09T09:41:14Z

commit 902fbbf429b8213232b18de0ddfd5c0f3851cb8f upstream. Earlier ASICs have strap information exported, and this is missing for NBIO 7.11.0. Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher Fixes: ca8c68142ad8 ("drm/amdgpu: add nbio 7.11 registers") Link: https://lore.kernel.org/r/20241118174611.10700-1-mario.limonciello@amd.com Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amdkfd: Update logic for CU occupancy calculations

2024-09-25T16:56:00Z

Currently, the code uses the IH_VMID_X_LUT register to map a queue's vmid to the corresponding PASID. This logic is racy since CP can update the VMID-PASID mapping anytime especially when there are more processes than number of vmids. Update the logic to calculate CU occupancy by matching doorbell offset of the queue with valid wave counts against the process's queues. Signed-off-by: Mukul Joshi Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

drm/amdgpu: fix spelling in amd_shared.h

2024-09-18T20:14:26Z

Fix spelling in documentation. Reviewed-by: Kent Russell Signed-off-by: Alex Deucher

drm/amdgpu/atomfirmware: Silence UBSAN warning

2024-09-10T17:44:29Z

Per the comments, these are variable sized arrays. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3613 Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher