<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/include/mes_v12_api_def.h, branch master</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=master</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=master'/>
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<updated>2026-01-27T23:08:35Z</updated>
<entry>
<title>drm/amd/include : Update MES v12 API header - SUSPEND</title>
<updated>2026-01-27T23:08:35Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2026-01-22T15:51:11Z</published>
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<id>urn:sha1:1bf8b4642c5f511dd73653a25ed7cd0470118389</id>
<content type='text'>
Update SUSPEND API to support sdma queues.
It's been supportted since 0x82 for gfx12

Signed-off-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include : Update MES v12 API header</title>
<updated>2025-12-16T18:23:10Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2025-06-19T16:40:46Z</published>
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<id>urn:sha1:2db0936438a044b9403dc69140226dfbf89b0b96</id>
<content type='text'>
Add LDS out of range reporting support in mes API

Signed-off-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Reviewed-by: Jonathan Kim &lt;jonathan.kim@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include : Update MES v12 comments on RESET API</title>
<updated>2025-12-16T18:18:59Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2025-11-04T16:27:12Z</published>
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<id>urn:sha1:2b950ac91314ee25daafd3be37ca12db2540f80f</id>
<content type='text'>
Added comments for the layout of contents that addressed by doorbell_offset_addr
in RESET API

Signed-off-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: include rrmt mode for mes_v12_1</title>
<updated>2025-12-08T19:11:56Z</updated>
<author>
<name>Alex Sierra</name>
<email>alex.sierra@amd.com</email>
</author>
<published>2025-03-07T18:17:34Z</published>
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<id>urn:sha1:f8692d2f9ae0a48bf378cc33717772c5f940ce0d</id>
<content type='text'>
Implement rrmt for misc read/write regs ops in mes_v12.
This covers LOCAL/REMOTE XCD and LOCAL/REMOTE AID.

v2: fix comments (Alex)

Signed-off-by: Alex Sierra &lt;alex.sierra@amd.com&gt;
Reviewed-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Reviewed-by: Michael Chen &lt;michael.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include : Update MES v12 API header</title>
<updated>2025-12-08T18:56:43Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2025-02-05T17:06:50Z</published>
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<id>urn:sha1:25f687de6735beb5627e3f4d1445e3c4ce4b67e1</id>
<content type='text'>
1. Add RRMT option support which will be used for remote die
   register access
2. Update set_hw_resource1 for cooperative mode support
3. Add full_sh_mem_config_data for xnack support

v2: squash in compilation fix

Signed-off-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update remove after reset flag for MES remove queue</title>
<updated>2025-10-13T18:14:36Z</updated>
<author>
<name>Jonathan Kim</name>
<email>jonathan.kim@amd.com</email>
</author>
<published>2025-06-18T14:45:55Z</published>
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<id>urn:sha1:72ea12f6be3bb57c2118189f7a7cfeb1f7c2748c</id>
<content type='text'>
Remove queue after reset flag is required to remove a queue that has
been successfully reset to clean up the MES' internal state.

Signed-off-by: Jonathan Kim &lt;jonathan.kim@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable MES lr_compute_wa by default</title>
<updated>2025-09-23T14:22:38Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2025-09-19T00:48:00Z</published>
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<id>urn:sha1:1fb710793ce2619223adffaf981b1ff13cd48f17</id>
<content type='text'>
The MES set resources packet has an optional bit 'lr_compute_wa'
which can be used for preventing MES hangs on long compute jobs.

Set this bit by default.

Co-developed-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Signed-off-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include : Update MES v12 API header(INV_TLBS)</title>
<updated>2025-08-27T17:57:51Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2025-07-04T16:30:10Z</published>
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<id>urn:sha1:e86a411b4293a1db58954ce7c99db9903d530b9f</id>
<content type='text'>
The requirement from driver side is to have an API that can do the
tlb invalidation on dedicate pasid since driver don't know the vmid
and process mapping.
Make the API generic to support different tlb invalidation related
request. Driver can specify pasid, vmid, hub_id and vm address range
need to be invalidated.
With this API the old INV_GART in MISC Op can be deprecated.

Signed-off-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include : Update MES v12 API for fence update</title>
<updated>2025-02-13T02:05:50Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2025-02-05T17:33:11Z</published>
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<id>urn:sha1:15d8c92f107c17c2e585cb4888c67873538f9722</id>
<content type='text'>
MES fence_value will be updated in fence_addr if API success,
otherwise upper 32 bit will be used to indicate error code.
In any case, MES will trigger an EOP interrupt with 0xb1 as
context id in the interrupt cookie

Signed-off-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include : MES v11 and v12 API header update</title>
<updated>2025-02-13T02:04:06Z</updated>
<author>
<name>Shaoyun Liu</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2025-02-05T18:16:45Z</published>
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<id>urn:sha1:1c687c0da9efb7c627793483a8927554764e7a55</id>
<content type='text'>
MES requires driver set cleaner_shader_fence_mc_addr
for cleaner shader support.

Signed-off-by: Shaoyun Liu &lt;shaoyun.liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
