<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/include/asic_reg/uvd, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2017-12-06T17:48:19Z</updated>
<entry>
<title>drm/amd/include:cleanup vega10 uvd header files.</title>
<updated>2017-12-06T17:48:19Z</updated>
<author>
<name>Feifei Xu</name>
<email>Feifei.Xu@amd.com</email>
</author>
<published>2017-11-23T03:09:07Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=5d735f83c2b06ba51f2fae6404da576c6847cb64'/>
<id>urn:sha1:5d735f83c2b06ba51f2fae6404da576c6847cb64</id>
<content type='text'>
Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h.

Signed-off-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add uvd enc registers in header</title>
<updated>2017-10-06T21:43:53Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2017-10-02T00:00:07Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d0e62855fa7aea4736297abcbe4f0777f1332883'/>
<id>urn:sha1:d0e62855fa7aea4736297abcbe4f0777f1332883</id>
<content type='text'>
Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-and-Tested-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Introduction of SI registers (v2)</title>
<updated>2016-11-11T15:21:07Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2016-10-26T15:58:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33'/>
<id>urn:sha1:de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33</id>
<content type='text'>
This introduces the SI registers in the amdgpu
driver style.

v2: squash duplicates fix

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: switch UVD code to use UVD_NO_OP for padding</title>
<updated>2016-08-24T20:25:05Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-08-23T13:12:21Z</published>
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<id>urn:sha1:c8b4f288f4276078f169a404e2d1ac1535f82b93</id>
<content type='text'>
Replace packet2's with packet0 writes to UVD_NO_OP.  The
value written to UVD_NO_OP does not matter.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add support for UVD_NO_OP register</title>
<updated>2016-08-24T20:25:04Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-08-22T21:58:14Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8dd31d74acc1371d143fd0b2795dc3d16fb47202'/>
<id>urn:sha1:8dd31d74acc1371d143fd0b2795dc3d16fb47202</id>
<content type='text'>
Writes to this register are the preferred way to do NOPs.

Bump the driver version as well.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement UVD VM mode for Stoney v2</title>
<updated>2016-07-29T18:36:57Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-06-23T10:11:46Z</published>
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<id>urn:sha1:0f30a397d9824cc81722d9912ae6ec9cec2b929b</id>
<content type='text'>
Starting with Stoney we support running UVD in VM mode as well.

v2: rebased, only enable on Polaris for now.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: handle more than 10 UVD sessions (v2)</title>
<updated>2016-05-05T00:20:23Z</updated>
<author>
<name>Arindam Nath</name>
<email>arindam.nath@amd.com</email>
</author>
<published>2016-04-12T11:46:15Z</published>
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<id>urn:sha1:c036554170fcc2238c32a7edd72c1b61b886428a</id>
<content type='text'>
Change History
--------------

v2:
- Make firmware version check correctly. Firmware
  versions &gt;= 1.80 should all support 40 UVD
  instances.
- Replace AMDGPU_MAX_UVD_HANDLES with max_handles
  variable.

v1:
- The firmware can handle upto 40 UVD sessions.

Signed-off-by: Arindam Nath &lt;arindam.nath@amd.com&gt;
Signed-off-by: Ayyappa Chandolu &lt;ayyappa.chandolu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add UVD 6.0 register headers</title>
<updated>2015-06-04T01:03:08Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-04-16T19:34:40Z</published>
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<id>urn:sha1:3b1e08cb29565d30d3bb87b26fefb126c1e00d89</id>
<content type='text'>
These are register headers for the UVD (Universal Video Decoder)
block on the GPU.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add UVD 5.0 register headers</title>
<updated>2015-06-04T01:03:08Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-04-16T19:34:14Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=7aa27c37739c1bea219b744b351c3a74f6eb6674'/>
<id>urn:sha1:7aa27c37739c1bea219b744b351c3a74f6eb6674</id>
<content type='text'>
These are register headers for the UVD (Universal Video Decoder)
block on the GPU.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add UVD 4.2 register headers</title>
<updated>2015-06-04T01:03:07Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-04-16T19:33:44Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=8630f839e0d0c439098b084d8867b82e3aa6084a'/>
<id>urn:sha1:8630f839e0d0c439098b084d8867b82e3aa6084a</id>
<content type='text'>
These are register headers for the UVD (Universal Video Decoder)
block on the GPU.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
