<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/include/asic_reg/smu, branch linux-4.17.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.17.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2018-02-19T19:17:49Z</updated>
<entry>
<title>drm/amd/pp: Export registers for read vddc on VI/Vega10</title>
<updated>2018-02-19T19:17:49Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-01-02T06:06:05Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=680731ade574e770e16f4488eb4217e8b8b13ffe'/>
<id>urn:sha1:680731ade574e770e16f4488eb4217e8b8b13ffe</id>
<content type='text'>
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add CI asics support to smumgr (v3)</title>
<updated>2017-09-26T17:06:57Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-09-08T11:34:33Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9f4b35411cfed96d4f9f092b2fed14905af84d89'/>
<id>urn:sha1:9f4b35411cfed96d4f9f092b2fed14905af84d89</id>
<content type='text'>
This ports support for CI asics (Bonaire, Hawaii)
to the powerplay smumgr

v2: warning fix (Alex)
v3: squash in fix for thermal (Tom)

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add a new register define for APU in VI.</title>
<updated>2017-03-30T03:54:06Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-03-17T08:21:55Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=1c622002b1aae6bf97be6f3c36203a61d8cc61cb'/>
<id>urn:sha1:1c622002b1aae6bf97be6f3c36203a61d8cc61cb</id>
<content type='text'>
the ixcurrent_pg_status addr is different between APU and DGPU.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: read hw register to check pg status.</title>
<updated>2017-02-13T17:43:04Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-02-08T09:17:55Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=254cd2e08dd0c44f9de6424f10390343a34b4f5a'/>
<id>urn:sha1:254cd2e08dd0c44f9de6424f10390343a34b4f5a</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add current_pg_status register define for smu7.1</title>
<updated>2017-02-08T22:20:22Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-01-25T04:17:59Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=cbd9262f80e71088c8758464f52a38c3c0299ff8'/>
<id>urn:sha1:cbd9262f80e71088c8758464f52a38c3c0299ff8</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Introduction of SI registers (v2)</title>
<updated>2016-11-11T15:21:07Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2016-10-26T15:58:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33'/>
<id>urn:sha1:de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33</id>
<content type='text'>
This introduces the SI registers in the amdgpu
driver style.

v2: squash duplicates fix

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:use smc_index_11 for VI</title>
<updated>2016-10-25T18:38:20Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2016-03-29T03:01:51Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=4bc10d168a419dc07194fdb93ccc4c8cad1788e4'/>
<id>urn:sha1:4bc10d168a419dc07194fdb93ccc4c8cad1788e4</id>
<content type='text'>
for VI smc, index_0 to index_8 are all not safe,
they may used by BIOS/FW, and index_11 is reserved
only for driver.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add Fiji smu 7.1.3 headers (v2)</title>
<updated>2015-08-17T20:50:25Z</updated>
<author>
<name>David Zhang</name>
<email>david1.zhang@amd.com</email>
</author>
<published>2015-07-08T11:13:25Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=d1c4dcfb76a0053ca7bcc90608b3699ac1e1b39d'/>
<id>urn:sha1:d1c4dcfb76a0053ca7bcc90608b3699ac1e1b39d</id>
<content type='text'>
v2: agd5f: prepare for release

Signed-off-by: David Zhang &lt;david1.zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add SMU 8.0 register headers</title>
<updated>2015-06-04T01:03:06Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-04-16T19:32:09Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=47e6898750169db73219f77fbe467ddacd5aabda'/>
<id>urn:sha1:47e6898750169db73219f77fbe467ddacd5aabda</id>
<content type='text'>
These are register headers for the SMU (System Management Unit)
block on the GPU.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add SMU 7.1.2 register headers</title>
<updated>2015-06-04T01:03:05Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-04-16T19:31:26Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=bc136e1329f65ad7cd33fdfdb182e72233b4dcb8'/>
<id>urn:sha1:bc136e1329f65ad7cd33fdfdb182e72233b4dcb8</id>
<content type='text'>
These are register headers for the SMU (System Management Unit)
block on the GPU.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
