kernel/drivers/gpu/drm/amd/display/include/dpcd_defs.h, branch master

drm/amd/display: Add FR skipping CTS functions

2026-01-27T23:10:33Z

1. To check whether Sink reaches maximum skipping number Reviewed-by: Robin Chen Signed-off-by: Jack Chang Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: PR error HPD_IRQ handling

2026-01-10T19:21:53Z

[Why & How] Add error handling for IRQ_HPD in Panel Replay Reviewed-by: Robin Chen Reviewed-by: Wenjing Liu Signed-off-by: Jack Chang Signed-off-by: Matthew Stewart Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: DPCD for Selective Update

2026-01-10T19:21:53Z

[Why&How] Add flow to read selective update related info from DPCD, and pass the info to DMUB. Reviewed-by: Robin Chen Reviewed-by: Wenjing Liu Signed-off-by: Jack Chang Signed-off-by: Matthew Stewart Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Support DRR granularity

2025-12-16T18:25:41Z

[Why&How] Support DRR granularity for coasting Vtotal calculation Reviewed-by: Robin Chen Reviewed-by: Wenjing Liu Signed-off-by: Weiguang Li Signed-off-by: Chenyu Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add panel replay enablement option and logic

2025-11-18T15:50:06Z

[Why&How] 1.Add flow to enable and configure panel replay enablement and configuration 2.Add registry key for enable option 3.Add replay version check to be compatible with freesync replay 4.Add AC/DC switch function to notify ac/dc change. 5.Add flow in set event function to check and decide Replay enable/disable Reviewed-by: Robin Chen Signed-off-by: Jack Chang Signed-off-by: Leon Huang Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Read Sink emission rate capability

2024-10-15T15:23:45Z

[WHY] To get sink emission rate information for future supported refresh rate calculation. Reviewed-by: ChunTao Tso Signed-off-by: Robin Chen Signed-off-by: Roman Li Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Send DP_TOTAL_LTTPR_CNT during detection if LTTPR is present

2024-06-25T18:15:45Z

[WHY] New register field added in DP2.1 SCR, needed for auxless ALPM [HOW] Echo value read from 0xF0007 back to sink Reviewed-by: Wenjing Liu Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Alex Hung Signed-off-by: Michael Strauss Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Read replay data from sink

2023-08-07T21:14:07Z

Read DP_SINK_PR_PIXEL_DEVIATION_PER_LINE and DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Add structs for Freesync Panel Replay

2023-08-07T21:12:49Z

In some instances, the GPU is transmitting repeated frame to the sink without any updates or changes in the content. These repeat transmission are wasteful, resulting in power draw in different aspects of the system 1. DCN is fetching the frame of data from DF/UMC/DRAM. This memory traffic prevents power down of parts of this HW path. 2. GPU is transmitting pixel data to the display through the main link of the DisplayPort interface. This prevents power down of both the Source transmitter (TX) and the Sink receiver (RX) The concepts of utilizing replay is similar to PSR, but there is a benefit of: Source and Sink remaining synchronized which allows for - lower latency when switching from replay to live frames - enable the possibility of more use cases - easy control of the sink's refresh rate during replay Due to Source and Sink remaining timing synchronized, Replay can be activated in more UI scenarios. Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: add support for three new square pattern variants from DP2.1 specs

2022-12-15T17:18:19Z

[why] DP2.1 specs has brought 3 new variants of sqaure patterns with different pre-shoot and de-emphasis equalization requirements. The commit adds logic to identify these variants and apply corresponding eqaulization requirements into hardware lane settings. Reviewed-by: George Shen Acked-by: Jasdeep Dhillon Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher