<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/display/dmub/src, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
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<updated>2025-11-04T16:53:20Z</updated>
<entry>
<title>drm/amd/display: Increase IB mem size</title>
<updated>2025-11-04T16:53:20Z</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2025-10-23T17:56:32Z</published>
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<id>urn:sha1:54963d18a8e99e3eb5fe39b73c83b66fe8caf43f</id>
<content type='text'>
[Why &amp; How]
Increase IB mem size to match size of largest structure that will
use IB transfer between driver and DMU.

Reviewed-by: Oleh Kuzhylnyi &lt;oleh.kuzhylnyi@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add dc interface to log pre os firmware information</title>
<updated>2025-10-28T13:58:11Z</updated>
<author>
<name>Meenakshikumar Somasundaram</name>
<email>meenakshikumar.somasundaram@amd.com</email>
</author>
<published>2025-10-15T18:45:43Z</published>
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<id>urn:sha1:fb3896c18b224f2aa9dd8a4f73e6ba23c52b9691</id>
<content type='text'>
[Why]
Pre os firmware information is useful to debug pre os to post os fw
transition issues.

[How]
Add dc interface dc_log_preos_dmcub_info() to log pre os firmware
information.

Reviewed-by: Cruise Hung &lt;cruise.hung@amd.com&gt;
Signed-off-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix DMUB reset sequence for DCN32</title>
<updated>2025-10-28T13:57:21Z</updated>
<author>
<name>Dillon Varone</name>
<email>Dillon.Varone@amd.com</email>
</author>
<published>2025-09-30T16:17:13Z</published>
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<id>urn:sha1:423ef48d41cbcfd5ee2039085d59e1f29b020ef4</id>
<content type='text'>
[WHY&amp;HOW]
Backport reset sequence fixes implemented on DCN401 to DCN32 to address
stability issues when resetting the DMUB.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Dillon Varone &lt;Dillon.Varone@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Control BW allocation in FW side</title>
<updated>2025-10-20T22:26:33Z</updated>
<author>
<name>Cruise Hung</name>
<email>Cruise.Hung@amd.com</email>
</author>
<published>2025-10-08T06:44:29Z</published>
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<id>urn:sha1:1319fb80b31cd56d31cb08a334f7c6033f9609ac</id>
<content type='text'>
[Why]
The BW allocation feature should be controlled in FW side.

[How]
Pass the control bit to FW boot option.

Reviewed-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Cruise Hung &lt;Cruise.Hung@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Driver implementation for cursor offloading to DMU</title>
<updated>2025-10-13T18:14:32Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2025-08-26T21:12:44Z</published>
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<id>urn:sha1:8e8691ecee8239634dd9a5f87655fba9bb1ee874</id>
<content type='text'>
[Why]
We require an interlock between driver and firmware for upcoming
features and given that this could possibly happen on any single
cursor programming call (and that we can't asynchronously wait for
firmware to respond because of it) we'd be regressing cursor performance
by at least an extra 40us per call.

When we could possibly have cursor update every 20us - 100s from high
frequency gaming mice this means that we'd be stuttering or dropping
updates and impacting overall cursor performance.

We want a solution that can:

1. Interlock between other firmware features
2. Not stall out or require the DMCUB lock for every single update

[How]
When cursor offloading is enabled and supported by an ASIC driver will
route the cursor programming through to DMU as part of the regular
DC stream cursor programming interfaces for attributes and position.

The atomic pipe programming version will not be updated: this will still
follow the existing programming path by keeping track of a field that
specifies when the register writes should be deferred to DMU.

Cursor locking is not required when cursor offload is in progress since
the updates are consolidated and processed by DMU once at the end
of the frame in a periodic manner.

The shared buffer the firmware queries from is allocated along with the
rest of the scratch state region in an area that's accessible by
both firmware and driver.

The size of the cursor offload (v1) state will not change, but it does
have a unique union per ASIC version with room for expansion if needed.

When firmware features notifying DMU of DRR updates are not enabled we
now send an explicit vtotal min/max update via driver to DMU firmware
whenever the vtotal max changes. This is to allow the cursor programming
to determine the appropriate latch update point offset from vupdate.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix DMCUB loading sequence for DCN3.2</title>
<updated>2025-09-15T20:57:21Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2025-08-08T14:26:22Z</published>
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<id>urn:sha1:18e755155caa57a6e6c4aa4a40b0db0fba015289</id>
<content type='text'>
[Why]
New sequence from HW for reset and firmware reloading has been
provided that aims to stabilize the reload sequence in the case the
firmware is hung or has outstanding requests.

[How]
Update the sequence to remove the DMUIF reset and the redundant
writes in the release.

Reviewed-by: Sreeja Golui &lt;sreeja.golui@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: track dpia support</title>
<updated>2025-08-27T17:57:49Z</updated>
<author>
<name>Ausef Yousof</name>
<email>Ausef.Yousof@amd.com</email>
</author>
<published>2025-07-30T20:08:10Z</published>
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<id>urn:sha1:90868205b6f21896a62bf99e92ad1fb55eda0e2d</id>
<content type='text'>
[why&amp;how]
initialize a flag to track if we previously
supported dpia and write that to boot options

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Meenakshikumar Somasundaram &lt;meenakshikumar.somasundaram@amd.com&gt;
Signed-off-by: Ausef Yousof &lt;Ausef.Yousof@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Reserve instance index notified by DMUB</title>
<updated>2025-08-27T17:57:49Z</updated>
<author>
<name>Cruise Hung</name>
<email>Cruise.Hung@amd.com</email>
</author>
<published>2025-08-11T13:03:13Z</published>
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<id>urn:sha1:8b715afa8f2d74e7f3be1d8b2ff23adb53986c1b</id>
<content type='text'>
[Why]
Reserve instance index notified by DMUB.

[How]
Add new variable for instance index.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Cruise Hung &lt;Cruise.Hung@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: limited pll vco w/a v2</title>
<updated>2025-08-04T18:40:13Z</updated>
<author>
<name>Jingwen Zhu</name>
<email>Jingwen.Zhu@amd.com</email>
</author>
<published>2025-07-14T08:18:19Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3df957517f8c17cd6c9be9c5a12979caf653a763'/>
<id>urn:sha1:3df957517f8c17cd6c9be9c5a12979caf653a763</id>
<content type='text'>
[Why/How]
The w/a will cause reboot black screen issue.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Jingwen Zhu &lt;Jingwen.Zhu@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Revert "Add a config flag for limited_pll_vco"</title>
<updated>2025-07-28T20:40:08Z</updated>
<author>
<name>Ovidiu Bunea</name>
<email>ovidiu.bunea@amd.com</email>
</author>
<published>2025-07-17T14:41:41Z</published>
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<id>urn:sha1:b86cba11889ec4b784bfffc0a9424e1aa5eea56b</id>
<content type='text'>
This reverts commit 82139760dcf7829ae2ca3f70442be9b53a0aff40.

[why &amp; how]
DMUB header changes should be submitted to firmware branch first and
allowed to propagate to driver. Currently, this change breaks linux
builds so need to revert it until it's ready.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Ovidiu Bunea &lt;ovidiu.bunea@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
