<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/display/dc/inc, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
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<updated>2026-02-26T23:01:38Z</updated>
<entry>
<title>drm/amd/display: Enable DAC in DCE link encoder</title>
<updated>2026-02-26T23:01:38Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2026-02-02T11:25:07Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=37acc302e4fc37324b3d295b1de6b399a2fe9a39'/>
<id>urn:sha1:37acc302e4fc37324b3d295b1de6b399a2fe9a39</id>
<content type='text'>
[ Upstream commit 4bd8b5f8bcb57b430c35494d8a2471ce5fd7661d ]

Ensure that the DAC output is enabled at the correct time by
moving it to the DCE link encoder similarly to how digital
outputs are enabled.

This also removes the call to DAC1EncoderControl from the DCE
HWSS, which always felt like it was a hacky solution.

Fixes: 0fbe321a93ce ("drm/amd/display: Implement DCE analog link encoders (v2)")
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Tested-by: Mauro Rossi &lt;issor.oruam@gmail.com&gt;
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Pass proper DAC encoder ID to VBIOS</title>
<updated>2026-02-26T23:00:58Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-12-06T02:31:02Z</published>
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<id>urn:sha1:495070f9a9e6330371144a0d255c748419264165</id>
<content type='text'>
[ Upstream commit 436d0d22aa7035a9f9b24fb14cd0e84d6571ea87 ]

Similarly to the analog_engine field, add a new	analog_id field
which contains the encoder ID of the analog encoder that
corresponds to the link encoder.

Previously, the default encoder ID of the link encoder was used,
which meant that we passed the wrong ID in case of DVI-I.

Fixes: 5834c33fd3f6 ("drm/amd/display: Add concept of analog encoders (v2)")
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'amd-drm-next-6.19-2025-12-02' of https://gitlab.freedesktop.org/agd5f/linux into drm-next</title>
<updated>2025-12-02T23:43:49Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2025-12-02T23:43:09Z</published>
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<id>urn:sha1:0692602defb0c273f80dec9c564ca50726404aca</id>
<content type='text'>
amd-drm-next-6.19-2025-12-02:

amdgpu:
- Unified MES fix
- SMU 11 unbalanced irq fix
- Fix for driver reloading on APUs
- pp_table sysfs fix
- Fix memory leak in fence handling
- HDMI fix
- DC cursor fixes
- eDP panel parsing fix
- Brightness fix
- DC analog fixes
- EDID retry fixes
- UserQ fixes
- RAS fixes
- IP discovery fix
- Add missing locking in amdgpu_ttm_access_memory_sdma()
- Smart Power OLED fix
- PRT and page fault fixes for GC 6-8
- VMID reservation fix
- ACP platform device fix
- Add missing vm fault handling for GC 11-12
- VPE fix

amdkfd:
- Partitioning fix

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patch.msgid.link/20251202220101.2039347-1-alexander.deucher@amd.com
</content>
</entry>
<entry>
<title>Merge tag 'v6.18-rc6' into drm-next</title>
<updated>2025-11-20T22:55:08Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2025-11-20T22:55:08Z</published>
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<id>urn:sha1:ce0478b02ed29465c1de3d03c3eea721355f9d2d</id>
<content type='text'>
Linux 6.18-rc6

Backmerge in order to merge msm next

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add pipe topology history to dc</title>
<updated>2025-11-18T15:51:24Z</updated>
<author>
<name>Nicholas Carbones</name>
<email>ncarbone@amd.com</email>
</author>
<published>2025-10-31T20:36:09Z</published>
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<id>urn:sha1:1a7322e985807e21d7b3e00b4138f0c69af863a8</id>
<content type='text'>
[Why]
There is no way to check pipe topology update history through a
dump.

[How]
Add a topology history structure to dc with snapshots of the most recent
pipe topology updates.

Reviewed-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Nicholas Carbones &lt;ncarbone@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: dynamically clock gate before and after prefetch</title>
<updated>2025-11-12T02:54:16Z</updated>
<author>
<name>Leo Chen</name>
<email>leo.chen@amd.com</email>
</author>
<published>2025-10-31T19:25:47Z</published>
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<id>urn:sha1:401f8f33adc7240baa72fa0fb68ea0552094ede9</id>
<content type='text'>
[Why]
An invalidation request arriving during prefetch can potentially hang
the system if dynamic clock gating is enabled and memory power requests
are disabled.

[How]
• Disable clock gating and enable memory power requests for the duration
of the prefetch.
• Turn on clock gating and disable memory power requests again after
prefetch is complete.

Limit the scope for DCN35 and DCN42 only.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Leo Chen &lt;leo.chen@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;jerry.zuo@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: To support Replay frame skip mode</title>
<updated>2025-11-12T02:54:15Z</updated>
<author>
<name>Chuntao Tso</name>
<email>chunttso@amd.com</email>
</author>
<published>2025-10-31T02:02:51Z</published>
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<id>urn:sha1:f3f48d6ce5089b183fdea025a8a7798a220168f6</id>
<content type='text'>
[Why &amp; How]
The change is to optimize the Replay power saving by
reducing the refresh rate with frame skipping mode

Reviewed-by: Robin Chen &lt;robin.chen@amd.com&gt;
Signed-off-by: Chuntao Tso &lt;chunttso@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;jerry.zuo@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add concept of analog encoders (v2)</title>
<updated>2025-10-28T14:09:03Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-09-26T18:01:50Z</published>
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<id>urn:sha1:5834c33fd3f6f2a26dd4d6d4bbc7b8ed1c2ac4aa</id>
<content type='text'>
Add a num_analog_stream_encoders field to indicate how many
analog stream encoders are present. When analog stream encoders
are present, create them.

Additionally, add an analog_engine field to link encoders and
search for supported analog encoders in the BIOS for each link.
When connecting an RGB signal, search for analog stream encoders.

The actual DCE analog link and stream encoder is going to be
added in a subsequent commit.

v2:
Add check to see if an analog engine is really supported.

Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Introduce MAX_LINK_ENCODERS (v2)</title>
<updated>2025-10-28T14:07:52Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-09-26T18:01:43Z</published>
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<id>urn:sha1:2394736e70665117ad78f208e794ea7df03c73f4</id>
<content type='text'>
We are going to support analog encoders as well, not just digital,
so we need to make space for them in various arrays.

v2: Fix typo.

Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add more DC HW state info to underflow logging</title>
<updated>2025-10-28T13:57:44Z</updated>
<author>
<name>Karen Chen</name>
<email>Karen.Chen@amd.com</email>
</author>
<published>2025-10-15T15:13:07Z</published>
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<id>urn:sha1:dbf58a9dad4d80286c5c17e199f595eb0dd3be5a</id>
<content type='text'>
[Why]
Debugging underflow issues frequently requires knowing the
HW state at the time of underflow. To enable capturing this
HW state information, interface functions are needed for the
various DC HW blocks.

[How]
This change adds the interface functions to read HW state for
the following DC HW blocks:
- HUBBUB
- HUBP
- DPP
- MPC
- OPP
- DSC
- OPTC
- DCCG

Reviewed-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Karen Chen &lt;Karen.Chen@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
