<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/drivers/gpu/drm/amd/display/dc/hubbub, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-rolling-stable'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2025-11-12T02:54:16Z</updated>
<entry>
<title>drm/amd/display: dynamically clock gate before and after prefetch</title>
<updated>2025-11-12T02:54:16Z</updated>
<author>
<name>Leo Chen</name>
<email>leo.chen@amd.com</email>
</author>
<published>2025-10-31T19:25:47Z</published>
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<id>urn:sha1:401f8f33adc7240baa72fa0fb68ea0552094ede9</id>
<content type='text'>
[Why]
An invalidation request arriving during prefetch can potentially hang
the system if dynamic clock gating is enabled and memory power requests
are disabled.

[How]
• Disable clock gating and enable memory power requests for the duration
of the prefetch.
• Turn on clock gating and disable memory power requests again after
prefetch is complete.

Limit the scope for DCN35 and DCN42 only.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Leo Chen &lt;leo.chen@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;jerry.zuo@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add more DC HW state info to underflow logging</title>
<updated>2025-10-28T13:57:44Z</updated>
<author>
<name>Karen Chen</name>
<email>Karen.Chen@amd.com</email>
</author>
<published>2025-10-15T15:13:07Z</published>
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<id>urn:sha1:dbf58a9dad4d80286c5c17e199f595eb0dd3be5a</id>
<content type='text'>
[Why]
Debugging underflow issues frequently requires knowing the
HW state at the time of underflow. To enable capturing this
HW state information, interface functions are needed for the
various DC HW blocks.

[How]
This change adds the interface functions to read HW state for
the following DC HW blocks:
- HUBBUB
- HUBP
- DPP
- MPC
- OPP
- DSC
- OPTC
- DCCG

Reviewed-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Karen Chen &lt;Karen.Chen@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Set wm_pending when disable stutter w/a used</title>
<updated>2025-09-23T14:31:58Z</updated>
<author>
<name>Dillon Varone</name>
<email>Dillon.Varone@amd.com</email>
</author>
<published>2025-09-10T20:55:23Z</published>
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<id>urn:sha1:c480d074b3ff27a8d582505dfd53c9b091b63d57</id>
<content type='text'>
[WHY&amp;HOW]
When stutter is disabled prior to watermark programming due to a w/a,
wm_pending should be returned as true.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Dillon Varone &lt;Dillon.Varone@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Disable stutter when programming watermarks on dcn32</title>
<updated>2025-09-23T14:26:10Z</updated>
<author>
<name>Dillon Varone</name>
<email>Dillon.Varone@amd.com</email>
</author>
<published>2025-09-15T15:22:52Z</published>
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<id>urn:sha1:c82b8f96eb972eb313e20ede5eb6617bc393c490</id>
<content type='text'>
[WHY&amp;HOW]
Reprogramming watermarks with stutter allowed can cause instability on
some ASICs. Disable it prior to raising watermarks (prepare bandwidth),
then re-enable after lowering (optimize bandwidth).

Reviewed-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Signed-off-by: Dillon Varone &lt;Dillon.Varone@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Adding interface to log hw state when underflow happens</title>
<updated>2025-08-04T18:40:32Z</updated>
<author>
<name>Muhammad Ahmed</name>
<email>Muhammad.Ahmed@amd.com</email>
</author>
<published>2025-07-25T01:50:25Z</published>
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<id>urn:sha1:5dc0ec782ef17ed10b87fa0962388040a86602c8</id>
<content type='text'>
[why]
Will help us better debug underflow issues.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Muhammad Ahmed &lt;Muhammad.Ahmed@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add skip rIOMMU dc config option</title>
<updated>2025-05-05T16:58:17Z</updated>
<author>
<name>Kevin Gao</name>
<email>kgao1003@amd.com</email>
</author>
<published>2025-04-17T19:37:06Z</published>
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<id>urn:sha1:18a77bda7a9b999dc6c04bf6d68b1fc89d8ed4d6</id>
<content type='text'>
[Why]
Need option to skip rIOMMU calls for dcn21.

[How]
Added rIOMMU dc config option and check for whether to skip
rIOMMU calls.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Kevin Gao &lt;kgao1003@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove unused hubbub1_toggle_watermark_change_req</title>
<updated>2025-02-13T02:03:03Z</updated>
<author>
<name>Dr. David Alan Gilbert</name>
<email>linux@treblig.org</email>
</author>
<published>2025-02-02T21:58:54Z</published>
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<id>urn:sha1:9ab737f3aeea29129903de6ddebf4bbce3ec0644</id>
<content type='text'>
hubbub1_toggle_watermark_change_req() last use was removed in 2017 by
commit b8fce2c9d773 ("drm/amd/display: Optimize programming front end")

Remove it.

Signed-off-by: Dr. David Alan Gilbert &lt;linux@treblig.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Allow reuse of of DCN4x code</title>
<updated>2025-02-13T02:03:01Z</updated>
<author>
<name>Dmytro</name>
<email>dmytro.laktyushkin@amd.com</email>
</author>
<published>2024-10-25T14:31:18Z</published>
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<id>urn:sha1:2739bd123782f9bedc39285b3965ff2b4b3e6411</id>
<content type='text'>
Remove the static qualifier to make it available for code sharing
with other components.

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Dmytro &lt;dmytro.laktyushkin@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix seamless boot sequence</title>
<updated>2025-02-03T17:13:38Z</updated>
<author>
<name>Lo-an Chen</name>
<email>lo-an.chen@amd.com</email>
</author>
<published>2025-01-17T09:56:25Z</published>
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<id>urn:sha1:e01f07cb92513ca4b9b219ab9caa34d607bc1e2d</id>
<content type='text'>
[WHY]
When the system powers up eDP with external monitors in seamless boot
sequence, stutter get enabled before TTU and HUBP registers being
programmed, which resulting in underflow.

[HOW]
Enable TTU in hubp_init.
Change the sequence that do not perpare_bandwidth and optimize_bandwidth
while having seamless boot streams.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Lo-an Chen &lt;lo-an.chen@amd.com&gt;
Signed-off-by: Paul Hsieh &lt;paul.hsieh@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable Request rate limiter during C-State on dcn401</title>
<updated>2024-11-20T14:39:42Z</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-11-01T14:51:02Z</published>
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<id>urn:sha1:89713ce5518eda6b370c7a17edbcab4f97a39f68</id>
<content type='text'>
[WHY]
When C-State entry is requested, the rate limiter will be disabled
which can result in high contention in the DCHUB return path.

[HOW]
Enable the rate limiter during C-state requests to prevent contention.

Cc: stable@vger.kernel.org # 6.11+
Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
